JP6087742B2 - 半導体装置、および、チップ識別子の設定方法 - Google Patents

半導体装置、および、チップ識別子の設定方法 Download PDF

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Publication number
JP6087742B2
JP6087742B2 JP2013126128A JP2013126128A JP6087742B2 JP 6087742 B2 JP6087742 B2 JP 6087742B2 JP 2013126128 A JP2013126128 A JP 2013126128A JP 2013126128 A JP2013126128 A JP 2013126128A JP 6087742 B2 JP6087742 B2 JP 6087742B2
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Japan
Prior art keywords
chip
identifier
semiconductor
setting
chip identifier
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JP2013126128A
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English (en)
Japanese (ja)
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JP2015001994A5 (https=
JP2015001994A (ja
Inventor
康宏 加藤
康宏 加藤
渉 落合
渉 落合
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Canon Inc
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Canon Inc
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Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2013126128A priority Critical patent/JP6087742B2/ja
Priority to US14/297,126 priority patent/US9536121B2/en
Publication of JP2015001994A publication Critical patent/JP2015001994A/ja
Publication of JP2015001994A5 publication Critical patent/JP2015001994A5/ja
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Publication of JP6087742B2 publication Critical patent/JP6087742B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
    • G06K7/10009—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves
    • G06K7/10366—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves the interrogation device being adapted for miscellaneous applications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
JP2013126128A 2013-06-14 2013-06-14 半導体装置、および、チップ識別子の設定方法 Active JP6087742B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013126128A JP6087742B2 (ja) 2013-06-14 2013-06-14 半導体装置、および、チップ識別子の設定方法
US14/297,126 US9536121B2 (en) 2013-06-14 2014-06-05 Semiconductor device and chip identifier setting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013126128A JP6087742B2 (ja) 2013-06-14 2013-06-14 半導体装置、および、チップ識別子の設定方法

Publications (3)

Publication Number Publication Date
JP2015001994A JP2015001994A (ja) 2015-01-05
JP2015001994A5 JP2015001994A5 (https=) 2016-07-07
JP6087742B2 true JP6087742B2 (ja) 2017-03-01

Family

ID=52018744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013126128A Active JP6087742B2 (ja) 2013-06-14 2013-06-14 半導体装置、および、チップ識別子の設定方法

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US (1) US9536121B2 (https=)
JP (1) JP6087742B2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170006976A (ko) * 2015-07-10 2017-01-18 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
KR102283330B1 (ko) * 2017-03-27 2021-08-02 삼성전자주식회사 반도체 소자
JP7621132B2 (ja) 2021-02-22 2025-01-24 キヤノン株式会社 メモリ制御回路およびその制御方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001084172A (ja) * 1999-09-10 2001-03-30 Nec Home Electronics Ltd 半導体記憶装置
JP4799157B2 (ja) * 2005-12-06 2011-10-26 エルピーダメモリ株式会社 積層型半導体装置
JP4887844B2 (ja) * 2006-03-13 2012-02-29 オムロン株式会社 監視システム、その端末装置、主制御装置、端末装置の登録方法およびプログラム
US8228173B2 (en) * 2006-06-22 2012-07-24 Sirit Inc. Interrogating radio frequency tags
US20090315686A1 (en) * 2007-10-16 2009-12-24 Rcd Technology, Inc. Rfid tag using encrypted value
US8130527B2 (en) * 2008-09-11 2012-03-06 Micron Technology, Inc. Stacked device identification assignment
JP5160396B2 (ja) * 2008-12-18 2013-03-13 株式会社日立製作所 半導体装置
WO2010134201A1 (ja) * 2009-05-22 2010-11-25 株式会社日立製作所 半導体装置
JP5150591B2 (ja) * 2009-09-24 2013-02-20 株式会社東芝 半導体装置及びホスト機器
JP2011081730A (ja) * 2009-10-09 2011-04-21 Elpida Memory Inc 半導体装置及びこれを備える情報処理システム
JP2011258266A (ja) 2010-06-08 2011-12-22 Sony Corp 半導体装置および集積型半導体装置
US8621131B2 (en) * 2011-08-30 2013-12-31 Advanced Micro Devices, Inc. Uniform multi-chip identification and routing system

Also Published As

Publication number Publication date
US9536121B2 (en) 2017-01-03
US20140368319A1 (en) 2014-12-18
JP2015001994A (ja) 2015-01-05

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