JP6049152B2 - 光結合層を有する発光素子およびその製造方法 - Google Patents
光結合層を有する発光素子およびその製造方法 Download PDFInfo
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- JP6049152B2 JP6049152B2 JP2015148888A JP2015148888A JP6049152B2 JP 6049152 B2 JP6049152 B2 JP 6049152B2 JP 2015148888 A JP2015148888 A JP 2015148888A JP 2015148888 A JP2015148888 A JP 2015148888A JP 6049152 B2 JP6049152 B2 JP 6049152B2
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/0004—Devices characterised by their operation
- H01L33/002—Devices characterised by their operation having heterojunctions or graded gap
- H01L33/0025—Devices characterised by their operation having heterojunctions or graded gap comprising only AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
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Description
本発明の一態様では、発光素子が、基板と、基板に隣接するp形半導体層と、p形半導体層に隣接する活性層と、活性層に隣接するn形半導体層と、を含む。発光素子は、n形又はp形半導体層のいずれかに隣接する光結合構造を含む。実施形態によっては、光結合構造のせいぜい一部はn形又はp形半導体層から形成される。
本発明の別の態様では、光結合層(又は構造)の形成方法が提供される。本明細書において提供される方法は、発光ダイオード(LED)等の発光素子用の光結合素子の形成に用いられてよい。特定の実装では、本明細書において提供される方法は、シリコン基板上にIII−V族半導体を有するLED用の光結合層の形成に用いられる。
本発明の別の態様では、発光素子形成システムが、基板を保持するための反応チャンバと、この反応チャンバと流体結合し、反応チャンバをパージ又は排気するように構成されるポンプシステムと、発光素子形成方法を実装する機械可読コードを実行するためのプロセッサを有するコンピュータシステムと、を含む。コードは、本明細書において提供される方法のいずれを実装してもよい。一実施形態では、コードは、反応チャンバ内に、1つ以上のIII−V族半導体材料を含む光結合層が上に配置される基板を提供することと、光結合層の一部の上に、光トランスミッタに隣接するn形半導体層及びp形半導体層のうちの一方と電気的に導通している電極を形成することと、を含む方法を実装する。別の実施形態では、コードは、反応チャンバ内に、バッファ層を有する基板を提供することと、光結合層を形成するためにバッファ層を粗面化することと、を含む方法を実装する。
Claims (12)
- 基板と、
前記基板上に位置し、銀を含む光反射層と、
前記光反射層上に位置するp形III−V族半導体層と、
前記p形III−V族半導体層上に位置する活性層と、
前記活性層上に位置するn形III−V族半導体層と、
前記n形III−V族半導体層上に位置する複数の光結合突起構造であって、そのそれぞれが、前記n形III−V族半導体層側から、前記n形III−V族半導体層の一部からなる第1層、及びアンドープ窒化ガリウムからなる第2層、を含むとともに、前記第1層及び前記第2層が当該それぞれの光結合突起構造の側面から露出する、複数の光結合突起構造と、
前記複数の光結合突起構造の一部の上に、前記複数の光結合突起構造の高さよりも厚く、前記複数の光結合突起構造の一部のうちの互いに隣する2つの光結合突起構造の間を埋め込んで構成され、当該互いに隣する2つの前記光結合突起構造のそれぞれの側面で前記第1層及び前記第2層に接触して設けられ、前記n形III−V族半導体層と電気的に接続された金属電極と、
を備え、
前記光結合突起形状は、前記活性層から前記n形III-V族半導体層に向かう方向において、その幅が狭くなる形状を有する、発光素子。 - 前記光結合突起構造は、100ナノメートル以上、2マイクロメートル以下の厚さを有する請求項1記載の発光素子。
- 前記第1層は、n形窒化ガリウムを含む請求項1または2に記載の発光素子。
- 前記第1層は、窒化アルミニウムガリウムを含む請求項1または2に記載の発光素子。
- 前記第1層は、窒化アルミニウムを含む請求項1または2に記載の発光素子。
- 前記光結合突起構造は、第3層を更に含み、
前記第2層は、前記第1層と前記第3層との間に位置する請求項1〜5のいずれか1つに記載の発光素子。 - 前記第3層は、窒化アルミニウムガリウム又は窒化アルミニウムを含む請求項6記載の発光素子。
- 前記光結合突起形状は、円錐またはピラミッド形状である請求項1〜7のいずれか1つに記載の発光素子。
- 前記光結合突起形状は、三角形断面を有する請求項1〜7のいずれか1つの記載の発光素子。
- 第1の基板上にアンドープ窒化ガリウム層を含むバッファ層を形成する工程と、
前記バッファ層上にn形窒化ガリウム層を形成する工程と、
前記n形窒化ガリウム層上に活性層を形成する工程と、
前記活性層上にp形III−V族半導体層を形成する工程と、
前記p形III−V族半導体層上に銀を含む光反射層を形成する工程と、
前記光反射層上に第2の基板を形成する工程と、
前記第1の基板を除去し、前記バッファ層を露出させる工程と、
前記バッファ層及び前記n形窒化ガリウム層の一部をウェットエッチング法により粗面化し、それぞれが前記活性層から前記n形窒化ガリウム層に向かう方向において、その幅が狭くなる形状を有し、それぞれが、前記n形窒化ガリウム層の一部からなる第1層及び前記アンドープ窒化ガリウム層からなる第2層を含む複数の光結合突起構造であって、前記第1層及び前記第2層が当該それぞれの光結合突起構造の側面から露出する、複数の光結合突起構造を形成する工程と、
前記複数の光結合突起構造の一部の上に、前記複数の光結合突起構造の高さよりも厚く、前記複数の光結合突起構造の一部のうち互いに隣する2つの光結合突起構造の間を埋め込んで、当該互いに隣する2つの光結合突起構造のそれぞれの側面で前記第1層及び前記第2層に接触し、前記n形窒化ガリウム層と電気的に接続された金属電極を形成する工程と、
を備える、発光素子の製造方法。 - 前記バッファ層は、前記第1の基板と前記アンドープ窒化ガリウム層との間に第3層を更に含み、
前記複数の光結合突起構造のそれぞれは、前記第3層を含んで形成される、請求項10記載の発光素子の製造方法。 - 前記第3層は、窒化アルミニウムガリウム又は窒化アルミニウムを含む請求項11記載の発光素子の製造方法。
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