JP6031060B2 - 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法 - Google Patents

半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法 Download PDF

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JP6031060B2
JP6031060B2 JP2014071458A JP2014071458A JP6031060B2 JP 6031060 B2 JP6031060 B2 JP 6031060B2 JP 2014071458 A JP2014071458 A JP 2014071458A JP 2014071458 A JP2014071458 A JP 2014071458A JP 6031060 B2 JP6031060 B2 JP 6031060B2
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insulating layer
semiconductor device
electrode
semiconductor element
metal wiring
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JP2014071458A
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Japanese (ja)
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JP2015195240A5 (https=
JP2015195240A (ja
Inventor
竹村　勝也
勝也 竹村
曽我　恭子
恭子 曽我
淺井　聡
聡 淺井
和紀 近藤
和紀 近藤
菅生　道博
道博 菅生
加藤　英人
英人 加藤
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Shin Etsu Chemical Co Ltd
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Shin Etsu Chemical Co Ltd
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Application filed by Shin Etsu Chemical Co Ltd filed Critical Shin Etsu Chemical Co Ltd
Priority to JP2014071458A priority Critical patent/JP6031060B2/ja
Priority to CN201910491197.6A priority patent/CN110176432B/zh
Priority to EP15773072.2A priority patent/EP3128549B1/en
Priority to PCT/JP2015/001367 priority patent/WO2015151417A1/ja
Priority to CN201580018116.0A priority patent/CN106165086B/zh
Priority to US15/126,172 priority patent/US10319653B2/en
Priority to KR1020167027164A priority patent/KR102338029B1/ko
Priority to TW104110258A priority patent/TWI648439B/zh
Publication of JP2015195240A publication Critical patent/JP2015195240A/ja
Publication of JP2015195240A5 publication Critical patent/JP2015195240A5/ja
Publication of JP6031060B2 publication Critical patent/JP6031060B2/ja
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    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
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    • H10W74/00—Encapsulations, e.g. protective coatings
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    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
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    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

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JP2014071458A 2014-03-31 2014-03-31 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法 Active JP6031060B2 (ja)

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KR1020167027164A KR102338029B1 (ko) 2014-03-31 2015-03-12 반도체장치, 적층형 반도체장치, 봉지후 적층형 반도체장치, 및 이들의 제조방법
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PCT/JP2015/001367 WO2015151417A1 (ja) 2014-03-31 2015-03-12 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法
CN201580018116.0A CN106165086B (zh) 2014-03-31 2015-03-12 半导体装置、积层型半导体装置、密封后积层型半导体装置以及这些装置的制造方法
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CN110176432B (zh) 2023-06-20
TW201602425A (zh) 2016-01-16
US10319653B2 (en) 2019-06-11
US20170103932A1 (en) 2017-04-13
JP2015195240A (ja) 2015-11-05
TWI648439B (zh) 2019-01-21
KR102338029B1 (ko) 2021-12-13
CN110176432A (zh) 2019-08-27
WO2015151417A1 (ja) 2015-10-08
CN106165086B (zh) 2019-12-06
EP3128549A4 (en) 2018-01-10
CN106165086A (zh) 2016-11-23
EP3128549B1 (en) 2021-09-01

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