JP6009300B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP6009300B2
JP6009300B2 JP2012213601A JP2012213601A JP6009300B2 JP 6009300 B2 JP6009300 B2 JP 6009300B2 JP 2012213601 A JP2012213601 A JP 2012213601A JP 2012213601 A JP2012213601 A JP 2012213601A JP 6009300 B2 JP6009300 B2 JP 6009300B2
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JP
Japan
Prior art keywords
layer
copper
wiring
tin alloy
via hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012213601A
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English (en)
Japanese (ja)
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JP2014067941A5 (enExample
JP2014067941A (ja
Inventor
清水　雄一郎
雄一郎 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2012213601A priority Critical patent/JP6009300B2/ja
Priority to US14/032,592 priority patent/US9232644B2/en
Publication of JP2014067941A publication Critical patent/JP2014067941A/ja
Publication of JP2014067941A5 publication Critical patent/JP2014067941A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/389—Improvement of the adhesion between the insulating substrate and the metal by the use of a coupling agent, e.g. silane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
JP2012213601A 2012-09-27 2012-09-27 配線基板及びその製造方法 Active JP6009300B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012213601A JP6009300B2 (ja) 2012-09-27 2012-09-27 配線基板及びその製造方法
US14/032,592 US9232644B2 (en) 2012-09-27 2013-09-20 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012213601A JP6009300B2 (ja) 2012-09-27 2012-09-27 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2014067941A JP2014067941A (ja) 2014-04-17
JP2014067941A5 JP2014067941A5 (enExample) 2015-10-08
JP6009300B2 true JP6009300B2 (ja) 2016-10-19

Family

ID=50337771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012213601A Active JP6009300B2 (ja) 2012-09-27 2012-09-27 配線基板及びその製造方法

Country Status (2)

Country Link
US (1) US9232644B2 (enExample)
JP (1) JP6009300B2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9418934B1 (en) * 2015-06-30 2016-08-16 International Business Machines Corporation Structure and fabrication method for electromigration immortal nanoscale interconnects
JP6625872B2 (ja) * 2015-11-25 2019-12-25 新光電気工業株式会社 配線基板及び配線基板の製造方法
EP3386282A4 (en) * 2015-11-30 2019-07-17 Toppan Printing Co., Ltd. MULTILAYER FITTED PCB AND METHOD FOR THE MANUFACTURE THEREOF
CN107347230B (zh) * 2016-05-06 2019-08-20 宏恒胜电子科技（淮安）有限公司 电路板的制备方法
WO2019171990A1 (ja) * 2018-03-09 2019-09-12 株式会社有沢製作所 積層体及びその製造方法
WO2021044274A1 (en) * 2019-09-03 2021-03-11 3M Innovative Properties Company Optical films and methods of manufacturing such optical films
US11393747B2 (en) * 2020-08-31 2022-07-19 Advanced Semiconductor Engineering, Inc. Substrate structure having roughned upper surface of conductive layer
TWI740767B (zh) * 2021-01-07 2021-09-21 欣興電子股份有限公司 線路板及其製作方法
WO2022202547A1 (ja) * 2021-03-22 2022-09-29 パナソニックＩｐマネジメント株式会社 配線体、実装基板、配線体の製造方法、及び、実装基板の製造方法
JP7569743B2 (ja) * 2021-04-19 2024-10-18 イビデン株式会社 配線基板

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS505375B1 (enExample) * 1970-03-26 1975-03-03
JPS61113296A (ja) 1984-11-08 1986-05-31 キヤノン株式会社 プリント回路板の製造方法
US6197688B1 (en) * 1998-02-12 2001-03-06 Motorola Inc. Interconnect structure in a semiconductor device and method of formation
JP3631682B2 (ja) 2001-02-26 2005-03-23 京セラ株式会社 多層配線基板及びその製造方法
US6475327B2 (en) * 2001-04-05 2002-11-05 Phoenix Precision Technology Corporation Attachment of a stiff heat spreader for fabricating a cavity down plastic chip carrier
CN100546435C (zh) 2003-11-14 2009-09-30 日立化成工业株式会社 金属层的树脂层的形成方法、印刷线路板及其制造方法
US7517736B2 (en) * 2006-02-15 2009-04-14 International Business Machines Corporation Structure and method of chemically formed anchored metallic vias
US8314348B2 (en) * 2008-03-03 2012-11-20 Ibiden Co., Ltd. Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
EP2200413A4 (en) * 2008-09-30 2011-12-14 Ibiden Co Ltd MULTI-LAYER PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING MULTI-LAYER PRINTED CIRCUIT BOARD
JP5310849B2 (ja) * 2009-06-24 2013-10-09 富士通株式会社 配線基板の製造方法
JP2011049289A (ja) * 2009-08-26 2011-03-10 Kyocera Corp 配線基板及びその製造方法
JP5330156B2 (ja) * 2009-08-26 2013-10-30 パナソニック株式会社 回路基板の製造方法、及び前記製造方法により得られた回路基板
US8324738B2 (en) * 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure

Also Published As

Publication number Publication date
US9232644B2 (en) 2016-01-05
JP2014067941A (ja) 2014-04-17
US20140083745A1 (en) 2014-03-27

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