JP5966009B2 - パッケージ基板に対するワイヤボンドなしでアセンブリ内の信号端子の２重の組を使用するスタブ最小化 - Google Patents

パッケージ基板に対するワイヤボンドなしでアセンブリ内の信号端子の２重の組を使用するスタブ最小化 Download PDF

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JP5966009B2
JP5966009B2 JP2014534602A JP2014534602A JP5966009B2 JP 5966009 B2 JP5966009 B2 JP 5966009B2 JP 2014534602 A JP2014534602 A JP 2014534602A JP 2014534602 A JP2014534602 A JP 2014534602A JP 5966009 B2 JP5966009 B2 JP 5966009B2
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grid
microelectronic
terminal
package
terminals
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JP2014530507A (ja
JP2014530507A5 (enExample
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クリスプ，リチャード・デューイット
ゾーニ，ワエル
ハーバ，ベルガセム
ランブレクト，フランク
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インヴェンサス・コーポレイション
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Priority claimed from US13/439,317 external-priority patent/US8659140B2/en
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    • H10W70/09—
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H10W70/60—
    • H10W70/65—
    • H10W70/68—
    • H10W72/00—
    • H10W90/00—
    • H10W70/654—
    • H10W70/655—
    • H10W72/29—
    • H10W72/59—
    • H10W72/834—
    • H10W72/853—
    • H10W72/859—
    • H10W72/879—
    • H10W72/932—
    • H10W72/942—
    • H10W72/944—
    • H10W72/9445—
    • H10W74/00—
    • H10W74/117—
    • H10W74/15—
    • H10W90/20—
    • H10W90/22—
    • H10W90/24—
    • H10W90/26—
    • H10W90/288—
    • H10W90/297—
    • H10W90/722—
    • H10W90/724—
    • H10W90/752—
    • H10W99/00—

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  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Wire Bonding (AREA)
JP2014534602A 2011-10-03 2012-09-26 パッケージ基板に対するワイヤボンドなしでアセンブリ内の信号端子の２重の組を使用するスタブ最小化 Expired - Fee Related JP5966009B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201161542553P 2011-10-03 2011-10-03
US61/542,553 2011-10-03
US201261600483P 2012-02-17 2012-02-17
US61/600,483 2012-02-17
US13/439,317 2012-04-04
US13/439,317 US8659140B2 (en) 2011-10-03 2012-04-04 Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
PCT/US2012/057204 WO2013052324A2 (en) 2011-10-03 2012-09-26 Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate

Related Child Applications (1)

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JP2016132320A Division JP2016195269A (ja) 2011-10-03 2016-07-04 パッケージ基板に対するワイヤボンドなしでアセンブリ内の信号端子の２重の組を使用するスタブ最小化

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JP2014530507A JP2014530507A (ja) 2014-11-17
JP2014530507A5 JP2014530507A5 (enExample) 2015-11-19
JP5966009B2 true JP5966009B2 (ja) 2016-08-10

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JP2014534602A Expired - Fee Related JP5966009B2 (ja) 2011-10-03 2012-09-26 パッケージ基板に対するワイヤボンドなしでアセンブリ内の信号端子の２重の組を使用するスタブ最小化
JP2014534599A Expired - Fee Related JP5964438B2 (ja) 2011-10-03 2012-09-26 パッケージ基板に対するワイヤボンドなしでアセンブリ内の信号端子の２重の組を使用するスタブ最小化
JP2016132320A Ceased JP2016195269A (ja) 2011-10-03 2016-07-04 パッケージ基板に対するワイヤボンドなしでアセンブリ内の信号端子の２重の組を使用するスタブ最小化

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JP2014534599A Expired - Fee Related JP5964438B2 (ja) 2011-10-03 2012-09-26 パッケージ基板に対するワイヤボンドなしでアセンブリ内の信号端子の２重の組を使用するスタブ最小化
JP2016132320A Ceased JP2016195269A (ja) 2011-10-03 2016-07-04 パッケージ基板に対するワイヤボンドなしでアセンブリ内の信号端子の２重の組を使用するスタブ最小化

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EP (2) EP2764512A2 (enExample)
JP (3) JP5966009B2 (enExample)
KR (2) KR20140081856A (enExample)
TW (4) TWI527188B (enExample)
WO (3) WO2013052321A2 (enExample)

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US9425237B2 (en) 2014-03-11 2016-08-23 Crossbar, Inc. Selector device for two-terminal memory
US9768234B2 (en) * 2014-05-20 2017-09-19 Crossbar, Inc. Resistive memory architecture and devices
US10211397B1 (en) 2014-07-07 2019-02-19 Crossbar, Inc. Threshold voltage tuning for a volatile selection device
US9633724B2 (en) 2014-07-07 2017-04-25 Crossbar, Inc. Sensing a non-volatile memory device utilizing selector device holding characteristics
US10115819B2 (en) 2015-05-29 2018-10-30 Crossbar, Inc. Recessed high voltage metal oxide semiconductor transistor for RRAM cell
US9698201B2 (en) 2014-07-09 2017-07-04 Crossbar, Inc. High density selector-based non volatile memory cell and fabrication
US9685483B2 (en) 2014-07-09 2017-06-20 Crossbar, Inc. Selector-based non-volatile cell fabrication utilizing IC-foundry compatible process
US9460788B2 (en) 2014-07-09 2016-10-04 Crossbar, Inc. Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor
US10079192B2 (en) * 2015-05-05 2018-09-18 Mediatek Inc. Semiconductor chip package assembly with improved heat dissipation performance
DE112015006937T5 (de) 2015-09-25 2018-09-06 Intel Corporation Verpackte integrierte Schaltkreisvorrichtung mit Vertiefungsstruktur
TWI615717B (zh) * 2016-01-25 2018-02-21 凌陽科技股份有限公司 高階製程晶片與低階製程晶片的資料傳輸方法以及使用其之積體電路
US20180005944A1 (en) * 2016-07-02 2018-01-04 Intel Corporation Substrate with sub-interconnect layer
US10607977B2 (en) 2017-01-20 2020-03-31 Google Llc Integrated DRAM with low-voltage swing I/O
US10096362B1 (en) 2017-03-24 2018-10-09 Crossbar, Inc. Switching block configuration bit comprising a non-volatile memory cell
JP7059970B2 (ja) * 2019-03-11 2022-04-26 株式会社デンソー 半導体装置
KR102026163B1 (ko) * 2019-07-02 2019-09-27 김복문 반도체 패키지의 배선 보정방법
TWI768294B (zh) 2019-12-31 2022-06-21 力成科技股份有限公司 封裝結構及其製造方法

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US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
JPH08186227A (ja) * 1995-01-05 1996-07-16 Hitachi Ltd 半導体装置及び電子装置
JPH1187640A (ja) * 1997-09-09 1999-03-30 Hitachi Ltd 半導体装置および電子装置
JP2000315776A (ja) * 1999-05-06 2000-11-14 Hitachi Ltd 半導体装置
JP3874062B2 (ja) * 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
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DE10139085A1 (de) * 2001-08-16 2003-05-22 Infineon Technologies Ag Leiterplattensystem, Verfahren zum Betreiben eines Leiterplattensystems, Leiterplatteneinrichtung und deren Verwendung, und Halbleitervorrichtung und deren Verwendung
KR100454123B1 (ko) * 2001-12-06 2004-10-26 삼성전자주식회사 반도체 집적 회로 장치 및 그것을 구비한 모듈
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Also Published As

Publication number Publication date
JP2014530507A (ja) 2014-11-17
TW201322412A (zh) 2013-06-01
WO2013052320A4 (en) 2013-07-11
EP2764513B1 (en) 2017-04-19
JP5964438B2 (ja) 2016-08-03
WO2013052324A3 (en) 2013-10-31
TW201639110A (zh) 2016-11-01
KR20140081856A (ko) 2014-07-01
TWI520284B (zh) 2016-02-01
WO2013052324A2 (en) 2013-04-11
TW201324708A (zh) 2013-06-16
TWI527188B (zh) 2016-03-21
TW201320297A (zh) 2013-05-16
WO2013052321A3 (en) 2013-10-17
EP2764512A2 (en) 2014-08-13
JP2015503214A (ja) 2015-01-29
WO2013052320A1 (en) 2013-04-11
KR20140073559A (ko) 2014-06-16
WO2013052321A2 (en) 2013-04-11
JP2016195269A (ja) 2016-11-17
TWI546930B (zh) 2016-08-21
EP2764513A2 (en) 2014-08-13

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