JP5951414B2 - 電子部品内蔵基板及び電子部品内蔵基板の製造方法 - Google Patents

電子部品内蔵基板及び電子部品内蔵基板の製造方法 Download PDF

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Publication number
JP5951414B2
JP5951414B2 JP2012188799A JP2012188799A JP5951414B2 JP 5951414 B2 JP5951414 B2 JP 5951414B2 JP 2012188799 A JP2012188799 A JP 2012188799A JP 2012188799 A JP2012188799 A JP 2012188799A JP 5951414 B2 JP5951414 B2 JP 5951414B2
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JP
Japan
Prior art keywords
substrate
layer
pad
metal
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012188799A
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English (en)
Japanese (ja)
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JP2014049477A5 (enExample
JP2014049477A (ja
Inventor
功一 田中
功一 田中
倉嶋　信幸
信幸 倉嶋
肇 飯塚
肇 飯塚
聡史 白木
聡史 白木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2012188799A priority Critical patent/JP5951414B2/ja
Priority to US13/969,814 priority patent/US9036362B2/en
Publication of JP2014049477A publication Critical patent/JP2014049477A/ja
Publication of JP2014049477A5 publication Critical patent/JP2014049477A5/ja
Application granted granted Critical
Publication of JP5951414B2 publication Critical patent/JP5951414B2/ja
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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2012188799A 2012-08-29 2012-08-29 電子部品内蔵基板及び電子部品内蔵基板の製造方法 Active JP5951414B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012188799A JP5951414B2 (ja) 2012-08-29 2012-08-29 電子部品内蔵基板及び電子部品内蔵基板の製造方法
US13/969,814 US9036362B2 (en) 2012-08-29 2013-08-19 Electronic component incorporated substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012188799A JP5951414B2 (ja) 2012-08-29 2012-08-29 電子部品内蔵基板及び電子部品内蔵基板の製造方法

Publications (3)

Publication Number Publication Date
JP2014049477A JP2014049477A (ja) 2014-03-17
JP2014049477A5 JP2014049477A5 (enExample) 2015-09-24
JP5951414B2 true JP5951414B2 (ja) 2016-07-13

Family

ID=50187323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012188799A Active JP5951414B2 (ja) 2012-08-29 2012-08-29 電子部品内蔵基板及び電子部品内蔵基板の製造方法

Country Status (2)

Country Link
US (1) US9036362B2 (enExample)
JP (1) JP5951414B2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11935819B2 (en) 2021-03-15 2024-03-19 Murata Manufacturing Co., Ltd. Circuit module having a plurality of lead frames connected to a substrate by metal posts

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140353824A1 (en) * 2013-05-29 2014-12-04 Huawei Technologies Co., Ltd. Package-on-package structure
KR20150025129A (ko) * 2013-08-28 2015-03-10 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
KR20150033937A (ko) 2013-09-25 2015-04-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제작 방법
JP6130312B2 (ja) * 2014-02-10 2017-05-17 新光電気工業株式会社 半導体装置及びその製造方法
US9679862B2 (en) * 2014-11-28 2017-06-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device having conductive bumps of varying heights
US9502368B2 (en) * 2014-12-16 2016-11-22 Intel Corporation Picture frame stiffeners for microelectronic packages
US20160190056A1 (en) * 2014-12-29 2016-06-30 SooSan Park Integrated circuit packaging system with package-on-package mechanism and method of manufacture thereof
JP6444269B2 (ja) * 2015-06-19 2018-12-26 新光電気工業株式会社 電子部品装置及びその製造方法
EP3376537A4 (en) * 2015-11-11 2019-04-17 KYOCERA Corporation PACKAGING FOR AN ELECTRONIC COMPONENT
KR101799668B1 (ko) * 2016-04-07 2017-11-20 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
JP7251951B2 (ja) 2018-11-13 2023-04-04 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US12310132B2 (en) 2019-05-15 2025-05-20 Sony Semiconductor Solutions Corporation Semiconductor package, semiconductor package manufacturing method, and electronic device
JP7421357B2 (ja) * 2020-02-05 2024-01-24 新光電気工業株式会社 部品内蔵基板及び部品内蔵基板の製造方法
US12148867B2 (en) * 2021-01-15 2024-11-19 Foshan Nationstar Optoelectronics Co., Ltd Light-emitting device and displayer
CN119325180B (zh) * 2023-07-17 2025-10-10 庆鼎精密电子（淮安）有限公司 电路板及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001217340A (ja) * 2000-02-01 2001-08-10 Nec Corp 半導体装置及びその製造方法
US7145226B2 (en) * 2003-06-30 2006-12-05 Intel Corporation Scalable microelectronic package using conductive risers
JP4182140B2 (ja) * 2005-12-14 2008-11-19 新光電気工業株式会社 チップ内蔵基板
EP1962342A4 (en) * 2005-12-14 2010-09-01 Shinko Electric Ind Co SUBSTRATE WITH BUILT-IN CHIP AND METHOD FOR PRODUCING THE SUBSTRATE WITH BUILT-IN CHIP
JP2009135398A (ja) * 2007-11-29 2009-06-18 Ibiden Co Ltd 組合せ基板
KR101711045B1 (ko) * 2010-12-02 2017-03-02 삼성전자 주식회사 적층 패키지 구조물

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11935819B2 (en) 2021-03-15 2024-03-19 Murata Manufacturing Co., Ltd. Circuit module having a plurality of lead frames connected to a substrate by metal posts

Also Published As

Publication number Publication date
US9036362B2 (en) 2015-05-19
US20140063764A1 (en) 2014-03-06
JP2014049477A (ja) 2014-03-17

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