JP5914613B2 - Mビットメモリセル用のm+nビットプログラミングおよびm+lビット読出し - Google Patents
Mビットメモリセル用のm+nビットプログラミングおよびm+lビット読出し Download PDFInfo
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5641—Multilevel memory having cells with different number of storage levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
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Description
上記のようなマルチレベルセルおよびシステムにおけるものを含むメモリ内の不揮発性メモリセルの閾値電圧は、一般的に、記憶値を示す範囲(「論理窓」、窓、Vt分布、閾値電圧レベル、または閾値状態とも呼ばれる)が割り当てられる。上記のように、一般的に、各範囲の間に、デッドスペースまたはマージン(余白、空隙、バッファ、緩衝用余白、緩衝領域または緩衝帯とも呼ばれる)が、論理窓のVt分布の重複を防止するために設けられる。これらの範囲つまり論理窓は、一般的に、メモリの動作において、それを表すデータ値および/または範囲つまりVt分布に割り当てられた公称閾値電圧レベルによって参照される。例えば、図6Aに詳細に示すように、2ビットセル型MLCの一例では、論理状態「11」、「01」、「10」および「00」を表すために4つの200mVの論理窓が各セルにおいて設定され、各状態の間には200mV〜400mVの緩衝領域が設けられている。このメモリの例では、論理状態「10」に対応するVt範囲が0.8V〜1.0Vに割り当てられており、公称閾値電圧レベルは0.9Vである。所定のVt論理窓に対する公称閾値電圧は、一般的に、メモリセルをその論理状態にプログラムするためにメモリセルに加えるべき目標電圧レベル(セルのバラツキやプログラミング過剰または不足のために正確には達成されないのが一般的であるが)として用いられる。不揮発性メモリを(例えば読出しまたは確認動作の一部として)読み出すつまり検出するときに、検出されたメモリセルの閾値電圧は、論理窓により規定される閾値電圧範囲(つまり対応する公称閾値電圧ないし論理状態)のうちの1つと照合される。これにより、メモリセルの状態をデジタルデータとして解釈することができ、その後に処理したりメモリセルから転送したりすることができる。
要求されるより高い閾値電圧分解能でメモリアレイ内のセルをプログラムし、および/または読み出すメモリデバイス、およびプログラミング、および/または読出し処理を説明した。これにより、不揮発性メモリセルのプログラミングにおいて、閾値電圧を、選択された状態/論理窓/閾値電圧範囲内で細かいステップでプログラムできるようになるので、プログラミング中に閾値電圧をより高い精度で設定できるようになると共に、次の隣接するメモリセルのプログラミングによるプログラム障害を予め補償できるようになる。つまり、次のメモリセルのプログラミングにより起きるプログラム障害によって、セルが、最終的に、選択された閾値電圧値またはその近似値となるようにする。これにより、その後に行われる任意のセルの読出し確認動作の精度が向上する。メモリセルの読出し検出において、閾値電圧分解能ないし細分度が高められると、メモリセルの実際のプログラム状態を、より高精度に解釈することができると共に、畳み込み符号化のような、メモリ全体のエラー率を下げる軟判定を行うために情報の付加的細分化を用いるデータ符号化復号化技術を、より有効に利用することができる。この構成は、その他の復号化技術、例えばPRML、トレリス符号変調、およびその他のLDPCやターボのような確率的復号化技術を用いる先進的符号で最適な復号化を達成することを可能とし、それによりメモリの全体的エラー率を低下させる。
Claims (14)
- メモリデバイスの作動方法であって、
第1のデータ値を、複数の論理窓状態を有するメモリセルの複数の目標閾値電圧のうちの1つに割り当てることと、
前記メモリセルを、前記目標閾値電圧のうちの1つにプログラムすることと、
を含み、
ここにおいて、前記複数の論理窓状態の数が、前記複数の目標閾値電圧の数より少なく、前記複数の論理窓状態の数が2のべき乗個であり、前記複数の目標閾値電圧の数が2のべき乗個ではない方法。 - 前記メモリセルがMビットのマルチレベルセルであり、前記複数の論理窓状態の数が、2のM乗個であることを含む請求項1の方法。
- 前記複数の目標閾値電圧の数が2のM乗個よりも多く、2の(M+1)乗個よりも少ないことを含む請求項2の方法。
- Mビットの入力データを受信することと、
前記入力データに追加データを加えて前記第1のデータ値を示すプログラムデータを生成することを含む請求項2又は3の方法。 - 前記メモリセルを、前記目標閾値電圧のうちの1つにプログラムする前に、前記プログラムデータをデジタルデータからアナログデータに変換することを含む請求項4の方法。
- 前記複数の論理窓状態は、前記メモリセルの利用可能な閾値電圧範囲内に、互いに隣接する2つの状態の間の閾値電圧の差が第1の値となるように設定された複数の状態であり、前記複数の目標閾値電圧の各々は、対応する閾値電圧範囲を有し、かつ、前記利用可能な閾値電圧範囲内に、互いに隣接する2つの閾値電圧範囲の間の閾値電圧の差が第2の値となるように設定されており、前記第1の値が前記第2の値よりも大きいことを含む請求項1乃至5のいずれかの方法。
- 前記複数の目標閾値電圧の数は、前記メモリセルの使用可能な、重複しないプログラミング範囲の最大数に等しい請求項1乃至6のいずれかの方法。
- 前記メモリセルから第2のデータ値を読み出すことをさらに含み、前記第2のデータ値のビット数が前記第1のデータ値のビット数と異なることを含む請求項1の方法
- 前記第2のデータ値のビット数が前記第1のデータ値のビット数よりも大きいことを含む請求項8の方法
- Mビットの入力データを受信することと、
前記入力データに第1の追加データを加えて前記第1のデータ値を示すプログラムデータを生成することと、
前記メモリセルから第2のデータ値を示すリードデータを読み出すことと、
前記リードデータから前記入力データと第2の追加データとを生成することと、
を含む請求項1の方法。 - 前記第2の追加データのビット数が前記第1の追加データのビット数と異なることを含む請求項10の方法。
- 前記第2の追加データのビット数が前記第1の追加データのビット数よりも大きいことを含む請求項10の方法。
- 前記リードデータをアナログデータからデジタルデータに変換して、前記入力データと前記第2の追加データとを生成することを含む請求項10の方法。
- 前記第2の追加データから前記入力データを復元することをさらに含む請求項10の方法。
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US11/943,916 | 2007-11-21 | ||
US11/943,916 US7633798B2 (en) | 2007-11-21 | 2007-11-21 | M+N bit programming and M+L bit read for M bit memory cells |
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JP5914613B2 true JP5914613B2 (ja) | 2016-05-11 |
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JP2014208130A Active JP5914613B2 (ja) | 2007-11-21 | 2014-10-09 | Mビットメモリセル用のm+nビットプログラミングおよびm+lビット読出し |
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US (3) | US7633798B2 (ja) |
EP (2) | EP3273443B1 (ja) |
JP (2) | JP2011504277A (ja) |
KR (1) | KR101125876B1 (ja) |
CN (2) | CN101868829B (ja) |
TW (2) | TWI402854B (ja) |
WO (1) | WO2009067448A1 (ja) |
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