JP5883346B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device. In particular, the present invention relates to a semiconductor memory device of a signal processing device in which a stored logic state does not disappear even when the power is turned off.

  A signal processing device such as a central processing unit (CPU) has various configurations depending on its application. In general, a signal processing device is provided with various storage devices such as a register and a cache memory in addition to a main memory for storing data and programs. The register has a role of temporarily holding a data signal for arithmetic processing, holding the execution state of the program, and the like. The cache memory is provided between the arithmetic device and the main memory, and is provided for the purpose of speeding up arithmetic processing by reducing access to the main memory.

  In a signal processing device, a storage device such as a register or a cache memory needs to write a data signal at a higher speed than the main memory. Therefore, a flip-flop or SRAM (Static Random Access Memory) is usually used as a register or cache memory. That is, for these registers, cache memories, and the like, volatile storage devices that lose data signals when supply of power supply voltage is interrupted are used.

  In order to suppress power consumption, a method has been proposed in which supply of power supply voltage to a signal processing device is temporarily stopped during a period in which no data signal is input / output (see, for example, Patent Document 1). In the method of Patent Document 1, a non-volatile storage device is arranged around a volatile storage device, and the data signal is temporarily stored in the non-volatile storage device.

JP 2010-124290 A

  In the configuration described in Patent Document 1, while the supply of the power supply voltage is stopped in the signal processing device, the data of the volatile storage device is transferred to and stored in a nonvolatile storage device arranged around the volatile storage device. be able to.

  However, since the volatile storage device and the nonvolatile storage device are operated separately, the data stored in the nonvolatile storage device before the supply of the power supply voltage is stopped and after the supply of the power supply voltage is restored. It is necessary to input another control signal for writing and reading data from the nonvolatile storage device. Accordingly, it is necessary to generate a control signal for writing data to the nonvolatile memory device and to read data from the nonvolatile memory device, and to provide wiring for supplying the signal.

  In view of the above problems, an embodiment of the present invention provides a semiconductor memory device in which the number of signals for controlling the semiconductor memory device can be reduced from an external circuit in a configuration in which power supply voltage is stopped and restored. Is one of the issues.

In one embodiment of the present invention, when a nonvolatile semiconductor memory device is used, a volatile memory device and a nonvolatile memory device are configured without being separated. Specifically, a semiconductor memory device includes a memory circuit including a transistor including an oxide semiconductor in a semiconductor layer, a capacitor element that accumulates charges for reading data held in the memory circuit, and accumulation of charges in the capacitor element. A charge storage circuit for controlling the data, a data detection circuit for controlling a data reading state, and a signal obtained by delaying the power supply voltage signal and the power supply voltage signal in a period immediately after the power supply voltage is supplied, A timing control circuit that generates a signal for controlling charge accumulation in the capacitor element by the charge storage circuit, and an inverter circuit that inverts and outputs the potential of one electrode of the capacitor element. is there. Then, even if the power supply voltage is stopped and restored by the data and the clock signal, the data is stored therein, and a semiconductor memory device which can be operated again is obtained.

  According to one embodiment of the present invention, a first transistor having a first terminal electrically connected to a data input line, a gate electrically connected to a clock signal line, an oxide semiconductor in a semiconductor layer, and one electrode Is electrically connected to the second terminal of the first transistor, and the gate is electrically connected to the second terminal of the first transistor and one electrode of the first capacitor. A memory circuit having a second transistor connected thereto, a second capacitor element for accumulating charges for reading data held in the memory circuit, and a power source potential line; A charge storage circuit for controlling charge storage in the second capacitor element, and a conduction state or a non-conduction state between one electrode of the second capacitor element and the first terminal of the second transistor. Data detection circuit and front In the first period in which the clock signal is supplied to the clock signal line, control is performed so that the charge storage circuit and the data detection circuit are alternately turned on according to the toggle operation of the clock signal, and In the second period immediately after the power supply voltage is supplied to the power supply potential line, the charge storage circuit supplies the second capacitor element with the signal of the power supply voltage and the signal obtained by delaying the signal of the power supply voltage. A semiconductor memory device having a timing control circuit that generates a signal for controlling charge accumulation and an inverter circuit that inverts and outputs the potential of one electrode of the second capacitor element.

  According to one embodiment of the present invention, a first transistor having a first terminal electrically connected to a data input line, a gate electrically connected to a clock signal line, an oxide semiconductor in a semiconductor layer, and one electrode Is electrically connected to the second terminal of the first transistor, and the gate is electrically connected to the second terminal of the first transistor and one electrode of the first capacitor. A memory circuit having a second transistor connected thereto, a second capacitor element for storing charges for reading data held in the memory circuit, and a first terminal electrically connected to a power supply potential line A charge storage circuit having a third transistor whose second terminal is electrically connected to one electrode of the second capacitor, and a first terminal electrically connected to one electrode of the second capacitor. Connected, and the second terminal is A data detection circuit having a fourth transistor electrically connected to the first terminal of the two transistors, and a toggle operation of the clock signal in a first period in which the clock signal is supplied to the clock signal line In the second period immediately after the power supply voltage is supplied to the power supply potential line, the power supply voltage signal is controlled so that the third transistor and the fourth transistor are alternately turned on. And a signal obtained by delaying the signal based on the power supply voltage to generate a signal for turning on the third transistor, and the potential of one electrode of the second capacitor element is inverted. And an inverter circuit that outputs the data.

In one embodiment of the present invention, the second transistor is preferably a semiconductor memory device including silicon in a semiconductor layer.

In one embodiment of the present invention, a semiconductor memory device in which the first transistor and the second transistor are stacked is preferable.

In one embodiment of the present invention, the data detection circuit includes one of the second capacitor elements depending on whether or not the charge stored in the second capacitor element is released based on a conduction state of the second transistor. A semiconductor memory device which is a circuit for converting the potential of the electrode into an inverted data signal obtained by inverting the data is preferable.

In one embodiment of the present invention, the circuit in which the signal of the power supply voltage is delayed is preferably a semiconductor memory device including a delay circuit and a buffer circuit.

In one embodiment of the present invention, the timing control circuit includes the NAND circuit to which the signal of the power supply voltage and a signal obtained by delaying the power supply voltage are input, an output signal of the NAND circuit, and the clock A semiconductor memory device including an OR circuit to which a signal is input is preferable.

  According to one embodiment of the present invention, data can be stored and output by a clock signal in a configuration in which power supply voltage is stopped and restored. In addition, the number of signals for controlling the semiconductor memory device can be reduced by making it possible to retain data when the power supply voltage is stopped without supplying another control signal from an external circuit.

1 is a circuit diagram of a semiconductor memory device. FIG. 11 is a circuit diagram for explaining a semiconductor memory device. FIG. 6 is a timing chart of the semiconductor memory device. 6A and 6B illustrate an operation of a semiconductor memory device. 6A and 6B illustrate an operation of a semiconductor memory device. 6A and 6B illustrate an operation of a semiconductor memory device. 1 is a diagram illustrating a configuration of a semiconductor memory device. The block diagram of a signal processing apparatus. 1 is a block diagram of a CPU using a semiconductor memory device. 10A and 10B illustrate a manufacturing process of a semiconductor memory device. 10A and 10B illustrate a manufacturing process of a semiconductor memory device. 10A and 10B illustrate a manufacturing process of a semiconductor memory device. FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor memory device. 6A and 6B illustrate a crystal structure of an oxide material according to one embodiment of the present invention. 6A and 6B illustrate a crystal structure of an oxide material according to one embodiment of the present invention. 6A and 6B illustrate a crystal structure of an oxide material according to one embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the configuration of the present invention can be implemented in many different modes, and it is easy for those skilled in the art to change the form and details in various ways without departing from the spirit and scope of the present invention. To be understood. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the structures of the present invention described below, the same reference numeral is used in different drawings.

  Note that the size, the layer thickness, the signal waveform, or the region of each structure illustrated in the drawings and the like in the embodiments is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale.

In addition, when it is explicitly described that A and B are connected, A and B are electrically connected, and A and B are functionally connected. , A and B are directly connected.

  Note that the terms “first”, “second”, “third” to “N” (N is a natural number) used in this specification are given to avoid confusion of components and are not limited numerically. I will add that.

(Embodiment 1)
The signal processing device has a semiconductor memory device. The signal processing device can store a 1-bit or multiple-bit data signal by using one or more semiconductor memory devices. In this embodiment, a structure of a semiconductor memory device in a signal processing device is described.

  The category of the signal processing device includes a CPU, a microprocessor, an image processing circuit, an LSI (Large Scale Integrated Circuit) such as a DSP (Digital Signal Processor), and an FPGA (Field Programmable Gate Array).

  FIG. 1A illustrates an example of a block diagram of a semiconductor memory device. A semiconductor memory device 100 of this embodiment mode illustrated in FIG. 1A is a circuit capable of holding and outputting input data D by a toggle operation of a clock signal CLK. In the configuration of the present embodiment, data D is captured at the timing when the clock signal is at the H level (high power supply potential VDD level), and data D is captured at the timing when the clock signal is at the L level (low power supply potential VSS level). Output as output signal Q. In addition, in the structure of this embodiment, even if the power supply voltage due to the high power supply potential VDD and the low power supply potential VSS (GND) is stopped at the timing when data is held, the data D captured in the semiconductor memory device is stored. The operation can be resumed from the output of the data D held when the power supply voltage is restored again.

Note that the stop of a signal or power supply voltage in this specification means that a signal or power supply voltage supplied to a wiring that supplies the signal or power supply voltage is not supplied. In this specification, the return of the signal or the power supply voltage refers to restarting the supply from the state where the supply of the signal or the power supply voltage supplied to the wiring for supplying the signal or the power supply voltage is stopped. In the present specification, “fixing a signal” refers to, for example, turning an AC signal oscillated at a predetermined frequency into a DC signal having a fixed potential of the high power supply potential VDD or the low power supply potential VSS.

  Next, a specific circuit configuration of the semiconductor memory device 100 is illustrated in FIG. A semiconductor memory device 100 illustrated in FIG. 1B includes a memory circuit 101 including a first capacitor 113, a second capacitor 102, a charge storage circuit 103 (also referred to as a precharge circuit), a data detection circuit 104, a timing A control circuit 105 and an inverter circuit 106 are included.

  FIG. 1B shows signals input to and output from the semiconductor memory device 100. In FIG. 1B, a first power supply potential line VDD that supplies a high power supply potential VDD, a second power supply potential line VSS that supplies a low power supply potential VSS, a data input line D that supplies data D, and a clock signal CLK. Are provided, and a clock signal line CLK for supplying the output signal Q and an output signal line Q for outputting the output signal Q are provided. In FIG. 1B, a delayed high power supply potential line VDD_delay for supplying a signal VDD_delay in which a rise in potential due to the supply of the high power supply potential VDD is delayed when the supply of the high power supply potential VDD is restored is provided. It has been.

  A memory circuit 101 illustrated in FIG. 1B includes a first transistor 111, a second transistor 112, and a first capacitor 113. One electrode (first terminal) of the source and drain of the first transistor 111 is connected to the data signal line D. The other electrode (second terminal) of the source and drain of the first transistor 111 is connected to the gate of the second transistor 112 and one electrode of the first capacitor 113. The gate of the first transistor 111 is connected to the clock signal line CLK. The other electrode of the first capacitor 113 is connected to the second power supply potential line VSS. Note that a node to which the first transistor 111, the second transistor 112, and the first capacitor 113 are connected is referred to as a “storage node D_HOLD” in the following description.

  The first transistor 111 takes the data D into the storage node D_HOLD in accordance with the toggle operation of the clock signal CLK supplied to the gate. For example, when the first transistor 111 is an n-channel transistor, when the clock signal CLK is at an H level, the first transistor 111 is turned on and data D is taken into the storage node D_HOLD. When the clock signal CLK is at the L level, the first transistor 111 is turned off, and the data D that has been captured immediately before is stored in the storage node D_HOLD.

  A first transistor 111 illustrated in FIG. 1B is a transistor in which a channel is formed in an oxide semiconductor layer. Note that in the drawings, the first transistor 111 is denoted by an OS symbol to indicate that a channel is formed in an oxide semiconductor layer.

An oxide semiconductor contains at least one element selected from In, Ga, Sn, and Zn. For example, an In—Sn—Ga—Zn—O-based oxide semiconductor that is an oxide of a quaternary metal, an In—Ga—Zn—O-based oxide semiconductor that is an oxide of a ternary metal, or In—Sn -Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based oxide semiconductor, Sn-Al-Zn -O-based oxide semiconductors, In-Zn-O-based oxide semiconductors that are binary metal oxides, Sn-Zn-O-based oxide semiconductors, Al-Zn-O-based oxide semiconductors, Zn-Mg -O-based oxide semiconductors, Sn-Mg-O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors, and In-O-based oxides of one-component metals An oxide semiconductor, a Sn—O-based oxide semiconductor, a Zn—O-based oxide semiconductor, or the like is used. Kill. Further, an element other than In, Ga, Sn, and Zn, for example, SiO ₂ may be included in the oxide semiconductor.

  For example, an In—Ga—Zn—O-based oxide semiconductor means an oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn), and there is no limitation on the composition ratio.

As the oxide semiconductor, a thin film represented by the chemical formula, InMO ₃ (ZnO) _m (m> 0) can be used. Here, M represents one or more metal elements selected from Zn, Ga, Al, Mn, and Co. For example, M includes Ga, Ga and Al, Ga and Mn, or Ga and Co.

In the case where an In—Zn—O-based material is used as the oxide semiconductor, the composition ratio of the target used is an atomic ratio, and In: Zn = 50: 1 to 1: 2 (in terms of the molar ratio, In ₂ O ₃ : ZnO = 25: 1 to 1: 4), preferably In: Zn = 20: 1 to 1: 1 (In ₂ O ₃ : ZnO = 10: 1 to 1: 2 in terms of molar ratio), More preferably, In: Zn = 1.5: 1 to 15: 1 (In ₂ O ₃ : ZnO = 3: 4 to 15: 2 in terms of molar ratio). For example, a target used for forming an In—Zn—O-based oxide semiconductor satisfies Z> 1.5X + Y when the atomic ratio is In: Zn: O = X: Y: Z.

  A transistor in which a channel is formed in a highly purified oxide semiconductor layer by thoroughly removing hydrogen in the oxide semiconductor layer has an off-current density of 100 zA / μm or less, preferably 10 zA / μm or less, More preferably, it can be 1 zA / μm or less. Therefore, this off-state current is significantly lower than the off-state current of a transistor using silicon having crystallinity. As a result, when the first transistor 111 is off, the potential of the storage node D_HOLD, that is, the potential of the gate of the second transistor 112 can be held for a long time.

  Note that the off-state current described in this specification refers to a current that flows between a source and a drain when a transistor is off. In an n-channel transistor (for example, a threshold voltage of about 0 to 2 V), a current flowing between a source and a drain when a voltage applied between the gate and the source is a negative voltage. .

  Note that in the above, a material that can realize off-state current characteristics equivalent to those of an oxide semiconductor material may be used instead of the oxide semiconductor material. For example, a wide gap material such as silicon carbide (more specifically, for example, a semiconductor material having an energy gap Eg larger than 3 eV) can be used. Alternatively, a structure may be employed in which the charge of the storage node D_HOLD is held for a long time by disconnecting a connection between wirings using a MEMS switch or the like instead of the transistor.

  A second transistor 112 illustrated in FIG. 1B is an element functioning as a switch. FIG. 1B illustrates an example in which a transistor of one conductivity type (for example, an n-channel type) is used. The switch here refers to one terminal of the switch corresponding to one of a source and a drain of the transistor, and the other terminal of the switch corresponding to the other of the source and the drain of the transistor. In addition, the conduction state or non-conduction state of the switch is selected by a potential based on data D held in the gate of the transistor. When the second transistor 112 which is an n-channel transistor functions as a switch, a conductive state (ON state) is selected by the H level and a non-conductive state (OFF state) is selected by the L level.

  In FIG. 1B, the second transistor 112 can be a transistor in which a channel is formed in a layer or substrate formed using a semiconductor other than an oxide semiconductor. For example, a transistor in which a channel is formed in a silicon layer or a silicon substrate can be used.

  Note that the first capacitor 113 can be omitted by using a capacitor formed by the gate of the second transistor 112 and one of the source and drain electrodes of the first transistor 111. is there.

Next, the second capacitor 102 shown in FIG. 1B selects the presence / absence of discharge of the charge accumulated in advance in one electrode according to the data D, and the potential corresponding to the charge changed according to the presence / absence of the discharge is inverted. The output signal Q is output via the circuit 106. Therefore, the second capacitor element has a first state in which charges are accumulated and a second state in which charge discharge is selected according to data D held in the storage node D_HOLD of the storage circuit 101. , Can be taken. Note that the node of one electrode of the second capacitor 102 is referred to as “storage node N_PRE” in the following description.

  A charge storage circuit 103 illustrated in FIG. 1B is a circuit for storing the charge in the storage node N_PRE of the second capacitor 102 to be in the first state. The charge storage circuit 103 includes a third transistor 114 which is an n-channel transistor. A first terminal of the third transistor 114 is connected to a first power supply potential line VDD that supplies a high power supply potential VDD. A second terminal of the third transistor 114 is connected to one electrode of the second capacitor. The gate of the third transistor 114 is connected to the timing control circuit 105, and a conduction state or a non-conduction state is controlled in accordance with a signal from the timing control circuit 105.

  A data detection circuit 104 illustrated in FIG. 1B is a circuit that controls conduction or non-conduction between the accumulation node N_PRE of the second capacitor 102 and the first terminal of the second transistor 112 in the memory circuit 101. is there. The data detection circuit 104 includes a fourth transistor 115 which is a p-channel transistor. A first terminal of the fourth transistor 115 is connected to one electrode of the second capacitor 102. The second terminal of the fourth transistor 115 is connected to the first terminal of the second transistor 112. The gate of the fourth transistor 115 is connected to the timing control circuit 105, and a conduction state or a non-conduction state is controlled in accordance with a signal from the timing control circuit 105.

  The timing control circuit 105 illustrated in FIG. 1B includes the charge accumulation circuit 103 and the charge storage circuit 103 in accordance with a toggle operation of the clock signal CLK in a period during which the clock signal CLK is supplied to the clock signal line CLK (also referred to as a first period). This is a circuit for controlling the data detection circuit 104 to be alternately in a conductive state. In addition, the timing control circuit 105 illustrated in FIG. 1B outputs a signal generated by the high power supply potential VDD in a period immediately after the high power supply potential VDD is supplied to the first power supply potential line VDD (also referred to as a second period). A circuit that generates a signal for controlling charge accumulation in the accumulation node N_PRE of the second capacitor by the charge accumulation circuit 103 based on a timing signal generated by a signal VDD_delay obtained by delaying a signal by the high power supply potential VDD. is there.

Note that the conductivity types of the third transistor 114 in the above-described charge storage circuit 103 and the fourth transistor 115 in the data detection circuit 104 are set so as to operate alternately. The third transistor 114 is an n-channel transistor which is turned on by a timing signal generated by a signal based on the high power supply potential VDD and a signal VDD_delay obtained by delaying the signal based on the high power supply potential VDD. This is because of control.

Note that FIG. 2 shows an example of a circuit for delaying a signal by the high power supply potential VDD. The circuit illustrated in FIG. 2 includes a delay circuit unit 201 and a buffer circuit unit 202. The delay circuit unit 201 may be configured by an RC delay circuit using the resistor element 203 and the capacitor element 204. The buffer circuit portion 202 may have a structure in which the n-channel transistor 205 is provided on the wiring side to which the high power supply potential VDD is supplied and the p-channel transistor 206 is provided on the wiring side to which the low power supply potential VSS is supplied. . In this way, the signal delay in the delay circuit unit 201 can be converted into the switching timing of the input to the buffer circuit unit 202 from the L level to the H level.

Here, FIG. 1B illustrates an example of a specific circuit configuration of the timing control circuit 105. In FIG. 1B, the timing control circuit 105 includes a NAND circuit 116 (negative logical product circuit) and an OR circuit 117 (logical sum circuit). The NAND circuit 116 receives a signal based on the high power supply potential VDD and a signal VDD_delay obtained by delaying the signal based on the high power supply potential VDD, and outputs a NAND circuit output signal NAND_OUT. The OR circuit 117 receives the NAND circuit output signal NAND_OUT and the clock signal CLK, and outputs an OR circuit output signal OR_OUT.

  An inverter circuit 106 illustrated in FIG. 1B is a circuit for converting the signal of the storage node N_PRE of the second capacitor 102 into an inverted signal and outputting the inverted signal. For the inverter circuit 106, for example, a circuit configuration in which a p-channel transistor and an n-channel transistor are combined may be used.

Next, in the operation of repeatedly holding and outputting data D, the operation of the semiconductor memory device 100 having the configuration of this embodiment when the supply of the power supply voltage is stopped and the supply of the power supply voltage is restored will be described. . FIG. 3 shows a timing chart of the semiconductor memory device shown in FIG. 1B and will be described with reference to the timing chart. In the timing chart of FIG. 3, VDD, VDD_delay, VSS, NAND_OUT, OR_OUT, D_HOLD, N_PRE, and Q correspond to the input / output signals and node potentials described in FIG. 3 illustrates a plurality of periods t1 to t6 using FIGS. 4 to 6 in order to describe a plurality of states that the semiconductor memory device 100 can take.

In the description with reference to FIG. 3 to FIG. 6, the data D is shown with numbers D1 to DN (N is a natural number) for each data. This is shown for explaining at what timing the data D taken in the semiconductor memory device 100 is output. Further, the signal of the storage node N_PRE in which a signal obtained by inverting the data D1 to DN is shown as inverted data D1_B to DN_B. Note that signals obtained by inverting the inverted data D1_B to DN_B become data D1 to DN.

Note that in the following description of the operation in FIG. 3, the conductivity type and logic circuit of each transistor are described as the structure illustrated in FIG. Note that the following description of the operation is not limited to this, and if the conduction state of each transistor is the same as in FIG. 3, the conductivity of each transistor, the combination of logic circuits, and the potential of each control signal should be set as appropriate. Can do. Each signal can be represented by an H level (high power supply potential VDD) and an L level (low power supply potential VSS).

  First, the operation in the first operation period T_ON1 in FIG. 3 in which the operation of repeatedly holding and outputting the data D is described. In the first operation period T_ON1, the period in which the data D1 is taken into the storage node D_HOLD from the data input line D and the clock signal CLK becomes H level by the toggle operation of the clock signal CLK (period t1 in FIG. 3) and the period t1 Thus, the data D1 taken into the storage node D_HOLD can be held, and the data D1 can be divided into periods (period t2 in FIG. 3) in which the data D1 is output from the output signal line as the output signal Q.

FIG. 4A is a diagram in which the transistor conduction state and the current flow that can be taken by the semiconductor memory device 100 in the period t1 of the first operation period T_ON1 are visualized by dotted arrows.

In the period t1, the clock signal CLK is at an H level, and the first transistor 111 in the memory circuit 101 is turned on. Therefore, the data D1 is supplied from the data input line D to the storage node D_HOLD. At this time, the conduction state of the second transistor 112 depends on the logic state of the data D1, and indicates “ON / OFF” in the drawing.

In the period t1, the first power supply potential line VDD and the delayed power supply potential line VDD_delay are at the H level. Therefore, NAND_OUT is at L level and OR_OUT is at H level. When OR_OUT becomes H level, the third transistor 114 in the charge accumulation circuit 103 is turned on, and the fourth transistor 115 in the data detection circuit 104 is turned off. As a result, the potential of the storage node N_PRE rises to the H level as the charge storage circuit 103 stores the charge. The output signal output via the inverter circuit 106 is at L level.

FIG. 4B is a diagram in which the transistor conduction state and the current flow that can be taken by the semiconductor memory device 100 in the period t2 of the first operation period T_ON1 are visualized by dotted arrows.

In the period t2, the clock signal CLK is at an L level, and the first transistor 111 in the memory circuit 101 is turned off. Therefore, even if the data input line D is data D2, the data D1 written in the previous period is held in the storage node D_HOLD. At this time, the conduction state of the second transistor 112 depends on the logic state of the data D1, and indicates “ON / OFF” in the drawing.

In the period t2, the first power supply potential line VDD and the delayed power supply potential line VDD_delay are at the H level. Therefore, NAND_OUT is at L level and OR_OUT is at L level. When OR_OUT becomes L level, the third transistor 114 in the charge accumulation circuit 103 is turned off, and the fourth transistor 115 in the data detection circuit 104 is turned on. As a result, the potential of the accumulation node N_PRE that has risen to the H level in the period t1 varies depending on the conduction state of the second transistor 112. Specifically, if the data D1 is at the H level, the second transistor 112 is turned on, the potential of the storage node N_PRE that has risen to the H level is lowered, and the data D1 is inverted to the L level. If the data D1 is at the L level, the second transistor 112 is turned off, the potential of the storage node N_PRE that has risen to the H level is held, and the data D1 becomes the inverted H level. That is, the storage node N_PRE becomes inverted data D1_B obtained by inverting the data D1. An output signal output through the inverter circuit 106 is D1 obtained by inverting the inverted data D1_B.

  Next, an operation for stopping the power supply voltage and an operation during the power supply voltage stop period T_OFF in FIG. 3 for holding the data D when the power supply voltage is stopped will be described. In the power supply stop period T_OFF, the data D and the clock signal CLK are set to the L level to store the data D4 held in the storage node D_HOLD (period t3 in FIG. 3), and stored in the storage node D_HOLD in the period t3. It can be divided into a period (period t4 in FIG. 3) in which the power supply voltage is stopped while the data D4 is held and the input / output signal is in an indefinite state.

3 to 6, in the hatched period “X”, an indeterminate state in which no signal is supplied based on the H-level or L-level power supply potential in the input / output signal and power supply voltage stop periods. Is the period.

FIG. 5A is a diagram in which the transistor conduction state and the current flow that the semiconductor memory device 100 can take in the power supply voltage stop period T_OFF period t3 are visualized by dotted arrows.

In the period t3, the clock signal CLK and the data D are at an L level, and the first transistor 111 in the memory circuit 101 is turned off. Therefore, even when the data input line D is at the L level, the data D4 written in the previous period is held in the storage node D_HOLD. At this time, the conduction state of the second transistor 112 depends on the logic state of the data D4, and “ON / OFF” is shown in the drawing.

In the period t3, the first power supply potential line VDD and the delayed power supply potential line VDD_delay are at the H level. Therefore, NAND_OUT is at L level and OR_OUT is at L level. When OR_OUT becomes L level, the third transistor 114 in the charge accumulation circuit 103 is turned off, and the fourth transistor 115 in the data detection circuit 104 is turned on. As a result, the potential of the storage node N_PRE that has risen to the H level in the immediately preceding period varies according to the conduction state of the second transistor 112. Specifically, if the data D4 is at the H level, the second transistor 112 is turned on, the potential of the storage node N_PRE that has increased to the H level is decreased, and the data D4 is inverted to the L level. If the data D4 is at the L level, the second transistor 112 is turned off, the potential of the storage node N_PRE that has been raised to the H level is held, and the data D4 is inverted to the H level. That is, the storage node N_PRE becomes inverted data D4_B obtained by inverting the data D4. An output signal output through the inverter circuit 106 is data D4 obtained by inverting the inverted data D4_B.

FIG. 5B is a diagram in which the transistor conduction state and the current flow that the semiconductor memory device 100 can take during the power supply voltage stop period T_OFF period t4 are visualized by dotted arrows.

In the period t4, the clock signal CLK is at an L level, the data D is in an indefinite state, and the first transistor 111 in the memory circuit 101 is in a non-conduction state. Therefore, the data D4 written in the previous period continues to be held in the storage node D_HOLD. At this time, the conduction state of the second transistor 112 depends on the logic state of the data D4, and “ON / OFF” is shown in the drawing.

In the period t4, the first power supply potential line VDD and the delayed power supply potential line VDD_delay are in an indefinite state. Therefore, the outputs of the NAND circuit 116 and the OR circuit 117 are indefinite. Therefore, NAND_OUT and OR_OUT are in an indefinite state. When OR_OUT becomes indefinite, the conduction state of the third transistor 114 in the charge storage circuit 103 and the fourth transistor 115 in the data detection circuit 104 becomes indefinite. Therefore, the potential of the storage node N_PRE is also in an indefinite state, and the output signal output via the inverter circuit 106 is also in an indefinite state.

  Next, the operation in the second operation period T_ON2 in FIG. 3 in which the power supply voltage is restored and the data D held when the power supply voltage is stopped will be described. In the second operation period T_ON2, the clock signal CLK is set to L level, the first power supply potential line VDD is set to H level, the delay power supply potential line VDD_delay is set to L level, and the potential of the storage node N_PRE is set to H level (FIG. 3). The period t5) can be divided into a period (period t6 in FIG. 3) in which the data D4 held in the storage node D_HOLD when the power supply voltage is stopped is output from the output signal line as the output signal Q.

FIG. 6A is a diagram in which the transistor conduction state and the current flow that can be taken by the semiconductor memory device 100 in the period t5 of the second operation period T_ON2 are visualized by dotted arrows.

In the period t5, the clock signal CLK and the data D are at an L level, and the first transistor 111 in the memory circuit 101 is turned off. Therefore, even when the data input line D is at the L level, the data D4 written immediately before the power supply voltage is stopped is held in the storage node D_HOLD. At this time, the conduction state of the second transistor 112 depends on the logic state of the data D4, and “ON / OFF” is shown in the drawing.

In the period t5, the first power supply potential line VDD is at the H level and the delay power supply potential line VDD_delay is at the L level. Therefore, NAND_OUT becomes H level and OR_OUT becomes H level. When OR_OUT becomes H level, the third transistor 114 in the charge accumulation circuit 103 is turned on, and the fourth transistor 115 in the data detection circuit 104 is turned off. As a result, the potential of the storage node N_PRE rises to the H level as the charge storage circuit 103 stores the charge. The output signal output via the inverter circuit 106 is at L level.

FIG. 6B is a diagram in which the transistor conduction state and the current flow that can be taken by the semiconductor memory device 100 in the period t6 of the second operation period T_ON2 are visualized by dotted arrows.

In the period t6, the clock signal CLK is at an L level, and the first transistor 111 in the memory circuit 101 is turned off. Therefore, even when the data input line D is data D5, the data D4 written immediately before the power supply voltage is stopped is held in the storage node D_HOLD. At this time, the conduction state of the second transistor 112 depends on the logic state of the data D4, and “ON / OFF” is shown in the drawing.

In the period t6, the first power supply potential line VDD and the delayed power supply potential line VDD_delay are at the H level. Therefore, NAND_OUT is at L level and OR_OUT is at L level. When OR_OUT becomes L level, the third transistor 114 in the charge accumulation circuit 103 is turned off, and the fourth transistor 115 in the data detection circuit 104 is turned on. As a result, the potential of the accumulation node N_PRE that has risen to the H level in the period t5 varies depending on the conduction state of the second transistor 112. Specifically, if the data D4 is at the H level, the second transistor 112 is turned on, the potential of the storage node N_PRE that has increased to the H level is decreased, and the data D4 is inverted to the L level. If the data D4 is at the L level, the second transistor 112 is turned off, the potential of the storage node N_PRE that has been raised to the H level is held, and the data D4 is inverted to the H level. That is, the storage node N_PRE becomes inverted data D4_B obtained by inverting the data D4. An output signal output through the inverter circuit 106 is data D4 obtained by inverting the inverted data D4_B.

  The above is the description of the operation of the semiconductor memory device 100.

  In the semiconductor memory device according to one embodiment of the present invention, before the supply of the power supply voltage is stopped and after the supply of the power supply voltage is restored, the volatile storage device and the nonvolatile storage device are not operated separately. It is possible to hold and read data. Further, the aforementioned data can be held and read without requiring control signals for data writing and data reading, and the number of signals for controlling the semiconductor memory device can be reduced.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 2)
In this embodiment, a structure in which a plurality of semiconductor memory devices 100 described in Embodiment 1 are used will be described.

  FIG. 7 shows an example of the structure of the semiconductor memory device in this embodiment. The semiconductor memory device illustrated in FIG. 7 includes an inverter circuit 401 connected to a high power supply potential VDD and a low power supply potential VSS, a semiconductor memory device group 403 including a plurality of semiconductor memory devices 402, and a delayed high power supply potential generation circuit 404. Have.

As each semiconductor memory device 402, the semiconductor memory device 100 having the structure described in Embodiment 1 can be used.

A high power supply potential VDD and a low power supply potential VSS are switched and applied to each semiconductor memory device 402 included in the semiconductor memory device group 403 by a selection signal SigA via an inverter circuit 401.

Each semiconductor memory device 402 included in the semiconductor memory device group 403 is connected to the delayed high power supply potential generation circuit 404 for generating the signal VDD_delay shown in FIG.

Further, each semiconductor memory device 402 included in the semiconductor memory device group 403 is supplied with the potential of the signal IN and the low power supply potential VSS.

With the above configuration, the high power supply potential VDD and the signal VDD_delay that is a signal obtained by delaying the high power supply potential VDD can be supplied to the plurality of semiconductor memory devices 100.

  This embodiment can be implemented in combination with any of the above embodiments as appropriate.

(Embodiment 3)
In this embodiment, a structure of a signal processing device using the semiconductor memory device described in Embodiment 1 is described.

  FIG. 8 illustrates an example of a signal processing device according to one embodiment of the present invention. The signal processing device includes at least one or more arithmetic devices and one or more semiconductor memory devices. Specifically, the signal processing device 150 illustrated in FIG. 8 includes an arithmetic device 151, an arithmetic device 152, a semiconductor memory device 153, a semiconductor memory device 154, a semiconductor memory device 155, a control device 156, and a power supply control circuit 157.

  The arithmetic device 151 and the arithmetic device 152 include a logic circuit that performs a simple logical operation, an adder, a multiplier, and various arithmetic devices. The semiconductor memory device 153 functions as a register that temporarily holds a data signal during arithmetic processing in the arithmetic device 151. The semiconductor memory device 154 functions as a register that temporarily holds a data signal during arithmetic processing in the arithmetic device 152.

  The semiconductor memory device 155 can be used as a main memory, and can store a program executed by the control device 156 as a data signal, or can store a data signal from the arithmetic device 151 and the arithmetic device 152.

  The control device 156 is a circuit that comprehensively controls the operations of the arithmetic device 151, the arithmetic device 152, the semiconductor memory device 153, the semiconductor memory device 154, and the semiconductor memory device 155 included in the signal processing device 150. 8 illustrates a configuration in which the control device 156 is a part of the signal processing device 150, the control device 156 may be provided outside the signal processing device 150.

  By using the semiconductor memory device described in Embodiment 1 for the semiconductor memory device 153, the semiconductor memory device 154, and the semiconductor memory device 155, supply of power supply voltage to the semiconductor memory device 153, the semiconductor memory device 154, and the semiconductor memory device 155 Even if the operation is stopped, the data signal can be held without increasing the number of signals to be controlled. Therefore, supply of power supply voltage to the entire signal processing device 150 can be stopped and power consumption can be suppressed. Alternatively, supply of power supply voltage to any one or more of the semiconductor memory device 153, the semiconductor memory device 154, and the semiconductor memory device 155 can be stopped to reduce power consumption of the signal processing device 150. In addition, after the supply of the power supply voltage is resumed, the state before the power supply stop can be restored in a short time.

  Further, as the supply of the power supply voltage to the semiconductor memory device is stopped, the supply of the power supply voltage to the arithmetic unit or the control circuit that exchanges data signals with the semiconductor memory device is stopped. good. For example, when no operation is performed in the arithmetic device 151 and the semiconductor memory device 153, the supply of power supply voltage to the arithmetic device 151 and the semiconductor memory device 153 may be stopped.

  The power supply control circuit 157 controls the magnitude of the power supply voltage supplied to the arithmetic device 151, the arithmetic device 152, the semiconductor memory device 153, the semiconductor memory device 154, the semiconductor memory device 155, and the control device 156 included in the signal processing device 150. To do. When the supply of the power supply voltage is stopped, the supply of the power supply voltage may be stopped by the power supply control circuit 157, or the arithmetic device 151, the arithmetic device 152, the semiconductor memory device 153, the semiconductor memory device 154, and the semiconductor A configuration performed in each of the storage device 155 and the control device 156 may be used.

  Note that a semiconductor memory device that functions as a cache memory may be provided between the semiconductor memory device 155 that is a main memory and the arithmetic device 151, the arithmetic device 152, and the control device 156. By providing the cache memory, it is possible to reduce the access to the main memory and speed up signal processing such as arithmetic processing. By using the above-described semiconductor memory device also for the semiconductor memory device functioning as a cache memory, the power consumption of the signal processing device 150 can be suppressed without increasing the number of signals to be controlled.

  This embodiment can be implemented in combination with any of the above embodiments as appropriate.

(Embodiment 4)
In this embodiment, a structure of a CPU which is one of signal processing devices according to one embodiment of the present invention will be described.

  FIG. 9 shows the configuration of the CPU of this embodiment. The CPUs shown in FIG. / F9920. The ALU is an Arithmetic logic unit, the Bus / I / F is a bus interface, and the ROM / I / F is a ROM interface. The ROM 9909 and the ROM • I / F9920 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 9 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application.

  Instructions input to the CPU via the Bus I / F 9908 are input to the Instruction Decoder 9903 and decoded, and then input to the ALU Controller 9902, the Interrupt Controller 9904, the Register Controller 9907, and the Timing Controller 0505.

  The ALU / Controller 9902, the Interrupt / Controller 9904, the Register / Controller 9907, and the Timing / Controller 9905 perform various controls based on the decoded instructions. Specifically, the ALU / Controller 9902 generates a signal for controlling the operation of the ALU 9901. The Interrupt Controller 9904 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The Register Controller 9907 generates an address of the Register 9906, and reads and writes the Register 9906 according to the state of the CPU.

  The Timing Controller 9905 generates signals that control the operation timings of the ALU 9901, ALU Controller 9902, Instruction Decoder 9903, Interrupt Controller 9904, and Register Controller 9907. For example, the Timing Controller 9905 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and inputs the clock signal CLK2 to the various circuits.

  In the CPU of this embodiment, the register 9906 is provided with a semiconductor memory device having the structure described in the above embodiment. The Register Controller 9907 can stop the supply of power supply voltage without increasing the number of signals to be controlled in the semiconductor memory device included in the Register 9906 in accordance with an instruction from the ALU 9901.

  In this manner, even when the operation of the CPU is temporarily stopped and the supply of the power supply voltage is stopped, the data signal can be held and power consumption can be reduced. Specifically, for example, the CPU can be stopped while the user of the personal computer stops inputting information to an input device such as a keyboard, thereby reducing power consumption.

  In this embodiment, the CPU has been described as an example. However, the signal processing device of the present invention is not limited to the CPU, and can be applied to LSIs such as a microprocessor, an image processing circuit, a DSP, and an FPGA.

  This embodiment can be implemented in combination with the above embodiment.

(Embodiment 5)
In the memory circuit 101 illustrated in FIG. 1B, the second transistor 112 in the case where the channel is formed in silicon, the first transistor 111 in which the channel is formed in the oxide semiconductor layer, and the first capacitor A method for manufacturing the semiconductor memory device 100 is described using the element 113 as an example.

  As shown in FIG. 10A, an insulating film 701 and a semiconductor film 702 separated from a single crystal semiconductor substrate are formed over a substrate 700.

  There is no particular limitation on a material that can be used as the substrate 700 as long as it has heat resistance enough to withstand heat treatment performed later. For example, as the substrate 700, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or the like manufactured by a fusion method or a float method can be used. As the glass substrate, a glass substrate having a strain point of 730 ° C. or higher is preferably used when the temperature of the subsequent heat treatment is high.

In this embodiment, a method for manufacturing the second transistor 112 will be described below by using an example in which the semiconductor film 702 is single crystal silicon. Note that a specific example of a method for manufacturing the single crystal semiconductor film 702 is briefly described. First, an ion beam made of ions accelerated by an electric field is injected into a bond substrate, which is a single-crystal semiconductor substrate, and the crystal structure is disturbed locally from the surface of the bond substrate to a region at a certain depth. An embrittled layer that is weakened is formed. The depth of the region where the embrittlement layer is formed can be adjusted by the acceleration energy of the ion beam and the incident angle of the ion beam. Then, the bond substrate and the substrate 700 over which the insulating film 701 is formed are attached to each other so that the insulating film 701 is sandwiched therebetween. In the bonding, after the bond substrate and the substrate 700 are overlapped, a part of the bond substrate and the substrate 700 is 1 N / cm ² or more and 500 N / cm ² or less, preferably 11 N / cm ² or more and 20 N / cm ² or less. Apply pressure. When pressure is applied, the bond substrate and the insulating film 701 start bonding from that portion, and finally, the bonding reaches the entire adhered surface. Next, by performing heat treatment, the microvoids existing in the embrittled layer are combined with each other, and the volume of the microvoids is increased. As a result, the single crystal semiconductor film which is part of the bond substrate in the embrittlement layer is separated from the bond substrate. The temperature of the heat treatment is set so as not to exceed the strain point of the substrate 700. Then, the semiconductor film 702 can be formed by processing the single crystal semiconductor film into a desired shape by etching or the like.

  In order to control the threshold voltage, an impurity element imparting p-type conductivity such as boron, aluminum, or gallium or an impurity element imparting n-type conductivity such as phosphorus or arsenic is added to the semiconductor film 702 You may do it. The addition of the impurity element for controlling the threshold voltage may be performed on the semiconductor film before patterning or may be performed on the semiconductor film 702 formed after patterning. Further, an impurity element for controlling the threshold voltage may be added to the bond substrate. Alternatively, the impurity element is added to the bond substrate in order to roughly adjust the threshold voltage, and then to the semiconductor film before patterning or by patterning in order to finely adjust the threshold voltage. This may also be performed for the semiconductor film 702.

  Note that although an example in which a single crystal semiconductor film is used is described in this embodiment, the present invention is not limited to this structure. For example, a polycrystalline, microcrystalline, or amorphous semiconductor film formed over the insulating film 701 by using a vapor deposition method may be used, or the semiconductor film may be crystallized by a known technique. Known crystallization methods include a laser crystallization method using laser light and a crystallization method using a catalytic element. Alternatively, a crystallization method using a catalytic element and a laser crystallization method can be used in combination. In addition, when using a substrate having excellent heat resistance such as quartz, a thermal crystallization method using an electric furnace, a lamp annealing crystallization method using infrared light, a crystallization method using a catalytic element, about 950 ° C. Alternatively, a crystallization method combining the high temperature annealing method may be used.

  Next, as illustrated in FIG. 10B, after a gate insulating film 703 is formed over the semiconductor film 702, a mask 705 is formed over the gate insulating film 703, and an impurity element imparting conductivity is added to the semiconductor film 702. By adding to a part of the impurity region, the impurity region 704 is formed.

The gate insulating film 703 can be formed by oxidizing or nitriding the surface of the semiconductor film 702 by performing high-density plasma treatment, heat treatment, or the like. The high-density plasma treatment is performed using, for example, a rare gas such as He, Ar, Kr, or Xe and a mixed gas such as oxygen, nitrogen oxide, ammonia, nitrogen, or hydrogen. In this case, high-density plasma can be generated at a low electron temperature by exciting the plasma by introducing a microwave. By oxidizing or nitriding the surface of the semiconductor film with oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by such high-density plasma, An insulating film having a thickness of 20 nm, preferably 5 to 10 nm can be formed in contact with the semiconductor film. For example, nitrous oxide (N ₂ O) is diluted 1 to 3 times (flow rate ratio) with Ar, and 3 to 5 kW microwave (2.45 GHz) power is applied at a pressure of 10 to 30 Pa to apply a semiconductor. The surface of the film 702 is oxidized or nitrided. By this treatment, an insulating film having a thickness of 1 nm to 10 nm (preferably 2 nm to 6 nm) is formed. Further, nitrous oxide (N ₂ O) and silane (SiH ₄ ) are introduced, and 3-5 kW microwave (2.45 GHz) power is applied at a pressure of 10-30 Pa, and silicon oxynitride is formed by vapor phase growth. A film is formed to form a gate insulating film. A gate insulating film having a low interface state density and an excellent withstand voltage can be formed by combining a solid phase reaction and a reaction by a vapor deposition method.

  Since the oxidation or nitridation of the semiconductor film by the high-density plasma treatment described above proceeds by a solid phase reaction, the interface state density between the gate insulating film 703 and the semiconductor film 702 can be extremely low. Further, by directly oxidizing or nitriding the semiconductor film 702 by high-density plasma treatment, variation in the thickness of the formed insulating film can be suppressed. Also, when the semiconductor film has crystallinity, the surface of the semiconductor film is oxidized by solid phase reaction using high-density plasma treatment, so that the rapid oxidation only at the crystal grain boundary is suppressed and the uniformity is good. A gate insulating film having a low interface state density can be formed. A transistor in which an insulating film formed by high-density plasma treatment is included in part or all of a gate insulating film can suppress variation in characteristics.

Further, by using a plasma CVD method, a sputtering method, or the like, silicon oxide, silicon nitride oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide or tantalum oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate with nitrogen added (HfSi _x O _y (x> 0, y> 0)), hafnium aluminate with nitrogen added (HfAl _x O _y (x> 0, y> 0) )) And the like may be a single layer or stacked to form the gate insulating film 703.

  Note that in this specification, oxynitride is a substance having a higher oxygen content than nitrogen in the composition, and nitride oxide has a nitrogen content higher than oxygen in the composition. Means a substance.

  The thickness of the gate insulating film 703 can be, for example, 1 nm to 100 nm, preferably 10 nm to 50 nm. In this embodiment, a single-layer insulating film containing silicon oxide is used as the gate insulating film 703 by a plasma CVD method.

  Next, after removing the mask 705, as shown in FIG. 10C, after removing a part of the gate insulating film 703 and forming an opening 706 in a region overlapping with the impurity region 704 by etching or the like, A gate electrode 707 and a conductive film 708 are formed.

  The gate electrode 707 and the conductive film 708 can be formed by forming a conductive film so as to cover the opening 706 and then processing (patterning) the conductive film into a predetermined shape. The conductive film 708 is in contact with the impurity region 704 in the opening 706. For the formation of the conductive film, a CVD method, a sputtering method, a vapor deposition method, a spin coating method, or the like can be used. As the conductive film, tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), or the like is used. it can. An alloy containing the above metal as a main component may be used, or a compound containing the above metal may be used. Alternatively, a semiconductor film such as polycrystalline silicon in which an impurity element such as phosphorus imparting conductivity is doped may be used.

  Note that although the gate electrode 707 and the conductive film 708 are formed using a single-layer conductive film in this embodiment, this embodiment is not limited to this structure. The gate electrode 707 and the conductive film 708 may be formed using a plurality of stacked conductive films.

  As a combination of the two conductive films, tantalum nitride or tantalum can be used for the first layer and tungsten can be used for the second layer. In addition to the above examples, tungsten nitride and tungsten, molybdenum nitride and molybdenum, aluminum and tantalum, aluminum and titanium, and the like can be given. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed in the step after forming the two-layer conductive film. Further, as a combination of two conductive films, for example, silicon and nickel silicide doped with an impurity element imparting n-type conductivity, silicon and tungsten silicide doped with an impurity element imparting n-type conductivity Etc. can also be used.

  In the case of a three-layer structure in which three conductive films are stacked, a stacked structure of a molybdenum film, an aluminum film, and a molybdenum film is preferably employed.

  In addition, a light-transmitting oxide conductive film such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, or zinc gallium oxide is used for the gate electrode 707 and the conductive film 708. Can also be used.

  Note that the gate electrode 707 and the conductive film 708 may be selectively formed by a droplet discharge method without using a mask. The droplet discharge method means a method of forming a predetermined pattern by discharging or ejecting droplets containing a predetermined composition from the pores, and includes an ink jet method and the like in its category.

  In addition, the gate electrode 707 and the conductive film 708 are formed by using an ICP (Inductively Coupled Plasma) etching method after forming the conductive film, and the etching conditions (the amount of power applied to the coil-type electrode layer, the substrate side) By appropriately adjusting the amount of power applied to the electrode layer, the electrode temperature on the substrate side, and the like, etching can be performed to have a desired tapered shape. Further, the taper shape can control the angle and the like depending on the shape of the mask. As an etching gas, a chlorine-based gas such as chlorine, boron chloride, silicon chloride, or carbon tetrachloride, a fluorine-based gas such as carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride, or oxygen can be used as appropriate. .

In the case where the oxide semiconductor layer 716 is formed by a sputtering method, water and hydrogen present in the deposition treatment chamber are reduced as much as possible. Specifically, the film formation chamber is heated before film formation, the water and / or hydrogen concentration in the gas introduced into the film formation chamber is reduced, and the backflow of gas exhausted from the film formation chamber is performed. It is preferable to prevent the above.

  Next, as illustrated in FIG. 10D, an impurity element imparting one conductivity is added to the semiconductor film 702 using the gate electrode 707 and the conductive film 708 as masks, so that a channel formation region 710 overlapping with the gate electrode 707 is formed. A pair of impurity regions 709 sandwiching the channel formation region 710 and an impurity region 711 in which an impurity element is further added to part of the impurity region 704 are formed in the semiconductor film 702.

  In this embodiment, the case where an impurity element imparting p-type conductivity (eg, boron) is added to the semiconductor film 702 is described as an example.

  Next, as illustrated in FIG. 11A, an insulating film 712 and an insulating film 713 are formed so as to cover the gate insulating film 703, the gate electrode 707, and the conductive film 708. Specifically, the insulating films 712 and 713 can be formed using an inorganic insulating film such as silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, or aluminum nitride oxide. In particular, it is preferable to use a low dielectric constant (low-k) material for the insulating films 712 and 713 because capacitance due to overlapping of various electrodes and wirings can be sufficiently reduced. Note that a porous insulating film using any of the above materials may be used for the insulating films 712 and 713. A porous insulating film has a lower dielectric constant than a high-density insulating film, so that parasitic capacitance caused by electrodes and wirings can be further reduced.

  In this embodiment, the case where silicon oxynitride is used for the insulating film 712 and silicon nitride oxide is used for the insulating film 713 is described as an example. Further, although the case where the insulating film 712 and the insulating film 713 are formed over the gate electrode 707 and the conductive film 708 is illustrated in this embodiment, the present invention is insulated over the gate electrode 707 and the conductive film 708. Only one layer may be formed, or a plurality of three or more insulating films may be stacked.

  Next, as illustrated in FIG. 11B, the surfaces of the gate electrode 707 and the conductive film 708 are exposed by performing CMP (Chemical Mechanical Polishing) treatment or etching treatment on the insulating film 712 and the insulating film 713. Note that the surfaces of the insulating film 712 and the insulating film 713 are preferably as flat as possible in order to improve characteristics of the first transistor 111 to be formed later.

  Through the above steps, the second transistor 112 can be formed.

  Next, a method for manufacturing the first transistor 111 is described. First, as illustrated in FIG. 11C, the oxide semiconductor layer 716 is formed over the insulating film 712 or the insulating film 713.

  The oxide semiconductor layer 716 can be formed by processing an oxide semiconductor film formed over the insulating film 712 and the insulating film 713 into a desired shape. The thickness of the oxide semiconductor film is 2 nm to 200 nm, preferably 3 nm to 50 nm, more preferably 3 nm to 20 nm. The oxide semiconductor film is formed by a sputtering method using an oxide semiconductor as a target. The oxide semiconductor film can be formed by a sputtering method in a rare gas (eg, argon) atmosphere, an oxygen atmosphere, or a rare gas (eg, argon) and oxygen mixed atmosphere.

  Note that before the oxide semiconductor film is formed by a sputtering method, reverse sputtering that generates plasma by introducing argon gas is performed to remove dust attached to the surfaces of the insulating films 712 and 713. Is preferred. Reverse sputtering is a method of modifying the surface by forming a plasma near the substrate by applying a voltage using an RF power source on the substrate side in an argon atmosphere without applying a voltage to the target side. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere. Alternatively, an argon atmosphere may be used in which oxygen, nitrous oxide, or the like is added. Alternatively, the reaction may be performed in an atmosphere in which chlorine, carbon tetrafluoride, or the like is added to an argon atmosphere.

  As described above, the oxide semiconductor film includes an In—Sn—Ga—Zn—O-based oxide semiconductor that is a quaternary metal oxide or an In—Ga—Zn—O that is a ternary metal oxide. Oxide semiconductor, In—Sn—Zn—O oxide semiconductor, In—Al—Zn—O oxide semiconductor, Sn—Ga—Zn—O oxide semiconductor, Al—Ga—Zn—O oxide Oxide semiconductor, Sn—Al—Zn—O-based oxide semiconductor, Hf—In—Zn—O-based oxide semiconductor, In—Zn—O-based oxide semiconductor that is a binary metal oxide, Sn—Zn— O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg-O-based oxide semiconductor, In-Mg-O-based oxide semiconductor, In-Ga- O-based oxide semiconductors, In-O based oxide semiconductors that are unitary metal oxides, Sn-O Oxide semiconductor, or the like can be used Zn-O-based oxide semiconductor.

Note that when an In—Sn—Zn—O-based oxide semiconductor is used as the oxide semiconductor film, the mobility of the transistor can be increased. In the case where an In—Sn—Zn—O-based oxide semiconductor is used, the threshold voltage of the transistor can be stably controlled. Note that in the case where an In—Sn—Zn—O-based oxide semiconductor is used, the composition ratio of the target to be used is an atomic ratio, In: Sn: Zn = 1: 2: 2, In: Sn: Zn = 2: 1: 3. In: Sn: Zn = 1: 1: 1 may be used.

  In this embodiment, a 30-nm-thick In—Ga—Zn—O-based oxide semiconductor thin film obtained by a sputtering method using a target containing In (indium), Ga (gallium), and Zn (zinc) is used. Used as an oxide semiconductor film. As the target, for example, the composition ratio of each metal is In: Ga: Zn = 1: 1: 0.5, In: Ga: Zn = 1: 1: 1, or In: Ga: Zn = 1: 1: 2. A target can be used. The filling rate of the target containing In, Ga, and Zn is 90% to 100%, preferably 95% to less than 100%. By using a target with a high filling rate, the formed oxide semiconductor film becomes a dense film.

In this embodiment, a substrate is held in a treatment chamber kept under reduced pressure, a sputtering gas from which hydrogen and moisture are removed is introduced while moisture remaining in the treatment chamber is removed, and an oxide semiconductor is formed using the above target. A film is formed. During film formation, the substrate temperature may be 100 ° C. or higher and 600 ° C. or lower, preferably 200 ° C. or higher and 400 ° C. or lower. By forming the film while heating the substrate, the concentration of impurities contained in the formed oxide semiconductor film can be reduced. Further, damage due to sputtering is reduced. In order to remove moisture remaining in the treatment chamber, an adsorption-type vacuum pump is preferably used. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means may be a turbo pump provided with a cold trap. When a processing chamber is exhausted using a cryopump, for example, a compound containing a hydrogen atom (more preferably a compound containing a carbon atom) such as a hydrogen atom or water (H ₂ O) is exhausted. The concentration of impurities contained in the formed oxide semiconductor film can be reduced.

  As an example of the film forming conditions, the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the direct current (DC) power supply power is 0.5 kW, and the oxygen (oxygen flow rate is 100%) atmosphere is applied. . Note that a pulse direct current (DC) power source is preferable because dust generated in film formation can be reduced and the film thickness can be made uniform.

Further, by setting the leak rate of the processing chamber of the sputtering apparatus to 1 × 10 ⁻¹⁰ Pa · m ³ / sec or less, impurities such as alkali metal and hydride to the oxide semiconductor film during the film formation by the sputtering method Can be reduced. Further, by using the above-described adsorption-type vacuum pump as an exhaust system, backflow of impurities such as alkali metal, hydrogen atom, hydrogen molecule, water, hydroxyl group, or hydride from the exhaust system can be reduced.

  In addition, when the purity of the target is 99.99% or higher, alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, hydrides, or the like mixed in the oxide semiconductor film can be reduced. In addition, when the target is used, the concentration of alkali metal such as lithium, sodium, or potassium can be reduced in the oxide semiconductor film.

  Note that in order to prevent the oxide semiconductor film from containing hydrogen, a hydroxyl group, and moisture as much as possible, a substrate in which the insulating film 712 and the insulating film 713 are formed in a preheating chamber of a sputtering apparatus as a pretreatment for film formation. 700 is preferably preheated, and impurities such as moisture or hydrogen adsorbed on the substrate 700 are desorbed and exhausted. Note that the preheating temperature is 100 ° C. or higher and 400 ° C. or lower, preferably 150 ° C. or higher and 300 ° C. or lower. In addition, a cryopump is preferable as the exhaust means provided in the preheating chamber. Note that this preheating treatment can be omitted. Further, this preheating may be similarly performed on the substrate 700 over which the conductive films 719 and 720 are formed before the gate insulating film 721 to be formed later.

Note that etching for forming the oxide semiconductor layer 716 may be dry etching or wet etching, or both of them may be used. As an etching gas used for dry etching, a gas containing chlorine (chlorine-based gas such as chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ), or the like) Is preferred. Gas containing fluorine (fluorine-based gas such as carbon tetrafluoride (CF ₄ ), sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ), trifluoromethane (CHF ₃ ), etc.), bromide Hydrogen (HBr), oxygen (O ₂ ), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, or the like can be used.

  As the dry etching method, a parallel plate RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. Etching conditions (such as the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, and the substrate-side electrode temperature) are adjusted as appropriate so that etching can be performed in a desired shape.

  As an etchant used for wet etching, a mixed solution of phosphoric acid, acetic acid, and nitric acid, or an organic acid such as citric acid or oxalic acid can be used. In this embodiment, ITO-07N (manufactured by Kanto Chemical Co., Inc.) is used.

  A resist mask for forming the oxide semiconductor layer 716 may be formed by an inkjet method. When the resist mask is formed by an ink-jet method, a manufacturing cost can be reduced because a photomask is not used.

  Note that before the conductive film in the next step is formed, reverse sputtering is preferably performed to remove a resist residue or the like attached to the surfaces of the oxide semiconductor layer 716, the insulating film 712, and the insulating film 713.

  Note that an oxide semiconductor film formed by sputtering or the like may contain a large amount of moisture or hydrogen (including a hydroxyl group) as an impurity. Since moisture or hydrogen easily forms a donor level, it is an impurity for an oxide semiconductor. Therefore, in one embodiment of the present invention, in order to reduce (dehydrate or dehydrogenate) impurities such as moisture or hydrogen in the oxide semiconductor film, the oxide semiconductor layer 716 is subjected to nitrogen or nitrogen in a reduced pressure atmosphere. Moisture content when measured using an inert gas atmosphere such as a rare gas, an oxygen gas atmosphere, or an ultra-dry air (CRDS (cavity ring down laser spectroscopy) type dew point meter) is 20 ppm (-55 in terms of dew point) ° C.) or less, preferably 1 ppm or less, preferably 10 ppb or less) The oxide semiconductor layer 716 is subjected to heat treatment under an atmosphere.

  By performing heat treatment on the oxide semiconductor layer 716, moisture or hydrogen in the oxide semiconductor layer 716 can be eliminated. Specifically, heat treatment may be performed at a temperature of 250 ° C. to 750 ° C., preferably 400 ° C. to less than the strain point of the substrate. For example, it may be performed at 500 ° C. for about 3 minutes to 6 minutes. When the RTA method is used for the heat treatment, dehydration or dehydrogenation can be performed in a short time, and thus the treatment can be performed even at a temperature exceeding the strain point of the glass substrate.

  In this embodiment, an electric furnace which is one of heat treatment apparatuses is used.

  Note that the heat treatment apparatus is not limited to an electric furnace, and may include a device for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, a rapid thermal annealing (RTA) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas that does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon, is used.

  In the heat treatment, it is preferable that moisture, hydrogen, or the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm). Or less, preferably 0.1 ppm or less).

Note that oxide semiconductors are insensitive to impurities, and there is no problem if the film contains considerable metal impurities, and inexpensive soda-lime glass containing a large amount of alkali metals such as sodium can also be used. (Kamiya, Nomura, Hosono, “Physical Properties of Amorphous Oxide Semiconductors and Current Status of Device Development”, Solid State Physics, September 2009, Vol. 44, pp. 621-633.). However, such an indication is not appropriate. An alkali metal is an impurity because it is not an element included in an oxide semiconductor. Alkaline earth metal is also an impurity when it is not an element constituting an oxide semiconductor. In particular, Na in the alkali metal diffuses into the insulating film and becomes Na ⁺ when the insulating film in contact with the oxide semiconductor layer is an oxide. In the oxide semiconductor layer, Na breaks or interrupts the bond between the metal and the oxygen included in the oxide semiconductor. As a result, for example, the transistor characteristics are deteriorated such as normally-on due to the shift of the threshold voltage in the negative direction and the mobility is lowered. In addition, the characteristics are also varied. The deterioration of the characteristics of the transistor and the variation in characteristics caused by the impurities are conspicuous when the hydrogen concentration in the oxide semiconductor layer is sufficiently low. Therefore, when the hydrogen concentration in the oxide semiconductor layer is 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁷ atoms / cm ³ or less, it is desirable to reduce the concentration of the impurity. Specifically, the measured value of Na concentration by secondary ion mass spectrometry is 5 × 10 ¹⁶ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or less, more preferably 1 × 10 ¹⁵ atoms / cm 3. It should be ³ or less. Similarly, the measured value of the Li concentration is 5 × 10 ¹⁵ atoms / cm ³ or less, preferably 1 × 10 ¹⁵ atoms / cm ³ or less. Similarly, the measured value of the K concentration is 5 × 10 ¹⁵ atoms / cm ³ or less, preferably 1 × 10 ¹⁵ atoms / cm ³ or less.

  Through the above steps, the concentration of hydrogen in the oxide semiconductor layer 716 can be reduced and the oxide semiconductor layer 716 can be highly purified. Accordingly, stabilization of the oxide semiconductor layer can be achieved. In addition, an oxide semiconductor layer with a wide band gap can be formed by heat treatment at a glass transition temperature or lower. Therefore, a transistor can be manufactured using a large-area substrate, and mass productivity can be improved. The heat treatment can be performed at any time after the oxide semiconductor layer is formed.

  Note that the oxide semiconductor layer may be amorphous or may have crystallinity. Even when a crystalline oxide semiconductor layer having a crystallinity is a crystalline oxide semiconductor having a c-axis orientation (also referred to as C Axis Crystalline Oxide Semiconductor: CAAC-OS), an effect of increasing the reliability of the transistor is obtained. Since it can obtain, it is preferable.

The CAAC-OS film is not completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film with a crystal-amorphous mixed phase structure where crystal parts and amorphous parts are included in an amorphous phase. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. Further, in the observation image obtained by a transmission electron microscope (TEM), the boundary between the amorphous part and the crystal part included in the CAAC-OS film is not clear. Further, a grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

In the crystal part included in the CAAC-OS film, the c-axis is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and triangular when viewed from the direction perpendicular to the ab plane. It has a shape or hexagonal atomic arrangement, and metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers as viewed from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, a simple term “perpendicular” includes a range from 85 ° to 95 °. In addition, a simple term “parallel” includes a range from −5 ° to 5 °.

Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, in the formation process of the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher in the vicinity of the surface. In addition, when an impurity is added to the CAAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film (formation surface) Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface). Note that the c-axis direction of the crystal part is parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

  Therefore, a transistor including an oxide semiconductor film including a CAAC-OS can reduce variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Thus, a transistor having stable electrical characteristics can be manufactured.

  The CAAC-OS can be manufactured by a sputtering method. It is important to form a hexagonal crystal in the initial stage of deposition of the CAAC-OS film by a sputtering method and to grow the crystal using the crystal as a seed. For that purpose, the distance between the target and the substrate is increased (for example, about 150 mm to 200 mm), and the substrate heating temperature is 100 ° C. to 500 ° C., preferably 200 ° C. to 400 ° C., more preferably 250 ° C. to 300 ° C. It is preferable.

In the case where a CAAC-OS film is formed by a sputtering method, a higher oxygen gas ratio in the atmosphere is preferable. For example, when the sputtering method is performed in a mixed gas atmosphere of argon and oxygen, the oxygen gas ratio is preferably 30% or more, and more preferably 40% or more. This is because replenishment of oxygen from the atmosphere promotes crystallization of the CAAC-OS.

In the case where a CAAC-OS film is formed by a sputtering method, the substrate on which the CAAC-OS film is formed is preferably heated to 150 ° C. or higher, and is preferably heated to 170 ° C. or higher. More preferred. This is because crystallization of the CAAC-OS is promoted as the substrate temperature rises.

Further, after heat treatment is performed on the CAAC-OS in a nitrogen atmosphere or in a vacuum, the heat treatment is preferably performed in an oxygen atmosphere or a mixed atmosphere of oxygen and another gas. This is because oxygen vacancies generated in the previous heat treatment can be restored by supplying oxygen from the atmosphere in the subsequent heat treatment.

In addition, the film surface (film formation surface) over which the CAAC-OS is formed is preferably flat. This is because the CAAC-OS has a c-axis that is substantially perpendicular to the deposition surface, and thus unevenness on the deposition surface induces generation of crystal grain boundaries in the CAAC-OS. . Therefore, it is preferable to perform planarization treatment such as chemical mechanical polishing (CMP) on the deposition surface before the CAAC-OS is formed. In addition, the average roughness of the deposition surface is preferably 0.5 nm or less, and more preferably 0.3 nm or less.

Here, the CAAC-OS will be described in detail with reference to FIGS. Unless otherwise specified, in FIGS. 14 to 16, the upward direction is the c-axis direction, and the plane orthogonal to the c-axis direction is the ab plane. Note that the upper half and the lower half simply refer to the upper half and the lower half when the ab surface is used as a boundary. In FIG. 14, O surrounded by a circle represents tetracoordinate O, and O surrounded by a double circle represents tricoordinate O.

FIG. 14A illustrates a structure including one hexacoordinate In and six tetracoordinate oxygen atoms adjacent to In (hereinafter, tetracoordinate O). A structure in which only one oxygen atom is adjacent to one In is referred to as a subunit here. The structure in FIG. 14A has an octahedral structure, but is illustrated as a planar structure for simplicity. Note that three tetracoordinate O atoms exist in each of an upper half and a lower half in FIG. The subunit shown in FIG. 14A has zero electric charge.

FIG. 14B illustrates one pentacoordinate Ga, three tricoordinate oxygen atoms close to Ga (hereinafter, tricoordinate O), and two tetracoordinates close to Ga. And a structure having O. All tricoordinate O atoms are present on the ab plane. One tetracoordinate O atom exists in each of an upper half and a lower half in FIG. In addition, since In also has five coordination, the structure illustrated in FIG. 14B can be employed. The subunit shown in FIG. 14B has zero electric charge.

FIG. 14C illustrates a structure including one tetracoordinate Zn and four tetracoordinate O adjacent to Zn. In FIG. 14C, there is one tetracoordinate O in the upper half, and three tetracoordinate O in the lower half. The subunit shown in FIG. 14C has zero electric charge.

FIG. 14D illustrates a structure including one hexacoordinate Sn and six tetracoordinate O adjacent to Sn. In FIG. 14D, there are three tetracoordinate O atoms in the upper half and three tetracoordinate O atoms in the lower half. The subunit shown in FIG. 14D has a charge of +1.

FIG. 14E illustrates a subunit including two Zn atoms. In FIG. 14E, there is one tetracoordinate O in the upper half, and one tetracoordinate O in the lower half. In the subunit illustrated in FIG. 14E, electric charge is -1.

Here, several aggregates of subunits are referred to as one group, and aggregates of a plurality of groups are referred to as one unit.

Here, a rule for combining these subunits will be described. The three Os in the upper half of hexacoordinate In each have three adjacent Ins in the downward direction, and the three Os in the lower half each have three adjacent Ins in the upper direction. One O in the upper half of pentacoordinate Ga has one adjacent Ga in the lower direction, and one O in the lower half has one adjacent Ga in the upper direction. One O in the upper half of tetracoordinate Zn has one neighboring Zn in the lower direction, and three Os in the lower half each have three neighboring Zn in the upper direction. In this way, the number of upward tetracoordinate O atoms of a metal atom is equal to the number of adjacent metal atoms in the downward direction of the O, and similarly the number of downward tetracoordinate O atoms of the metal atom is , The number of adjacent metal atoms in the upper direction of O is equal. Since O is 4-coordinate, the sum of the number of adjacent metal atoms in the downward direction and the number of adjacent metal atoms in the upward direction is 4. Therefore, when the sum of the number of tetracoordinate O atoms in the upward direction of a metal atom and the number of tetracoordinate O atoms in the downward direction of another metal atom is four, Subunits can be joined together. For example, in the case where a hexacoordinate metal atom (In or Sn) is bonded via tetracoordinate O in the lower half, since there are three tetracoordinate O atoms, a pentacoordinate metal atom (Ga or In) and any of four-coordinate metal atoms (Zn).

The metal atoms having these coordination numbers are bonded via tetracoordinate O in the c-axis direction. In addition, the subunits are combined to form one group so that the total charge of the layer structure is zero.

FIG. 15A is a model diagram of one group included in an In—Sn—Zn—O-based layer structure. FIG. 15B shows a unit composed of three groups. Note that FIG. 15C illustrates an atomic arrangement in the case where the layered structure in FIG. 15B is observed from the c-axis direction.

In FIG. 15A, for simplicity, tricoordinate O is omitted, and tetracoordinate O is only the number. For example, three tetracoordinates are provided in each of the upper half and the lower half of the Sn atom. The presence of O is shown as 3 in a round frame. Similarly, in FIG. 15A, one tetracoordinate O atom exists in each of the upper half and the lower half of the In atom, which is shown as 1 in a round frame. Similarly, in FIG. 15A, the lower half includes one tetracoordinate O atom, the upper half includes three tetracoordinate O atoms, and the upper half includes 1 atom. There are four tetracoordinate O atoms, and the lower half shows a Zn atom with three tetracoordinate O atoms.

In FIG. 15A, the group constituting the In—Sn—Zn—O-based layer structure includes three tetracoordinate O atoms in the upper half and the lower half in order from the top. Are bonded to In atoms in the upper half and the lower half one by one, and the In atoms are bonded to Zn atoms having three tetracoordinate O atoms in the upper half. Three tetracoordinate O atoms are bonded to In atoms in the upper half and the lower half through one tetracoordinate O atom, and the In atom is bonded to one tetracoordinate O atom in the upper half. It binds to a subunit consisting of two Zn atoms, and three tetracoordinate O atoms bind to Sn atoms in the upper half and lower half through one tetracoordinate O in the lower half of this subunit. It is the composition which is. A plurality of these groups are combined to form a unit.

Here, in the case of tricoordinate O and tetracoordinate O, the charges per bond can be considered to be −0.667 and −0.5, respectively. For example, the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Sn (5-coordinate or 6-coordinate) are +3, +2, and +4, respectively. Therefore, the subunit including Sn has a charge of +1. Therefore, in order to form a layer structure including Sn, a charge −1 that cancels the charge +1 is required. As a structure with charge −1, a subunit containing two Zn atoms can be given as shown in FIG. For example, if there is one subunit containing Sn and one subunit containing two Zn, the charge is canceled out, so the total charge of the layer structure can be zero.

Specifically, by repeating the unit illustrated in FIG. 15B, an In—Sn—Zn—O-based crystal (In ₂ SnZn ₃ O ₈ ) can be obtained. Note that an In—Sn—Zn—O-based layer structure obtained can be represented by a composition formula, In ₂ SnZn ₂ O ₇ (ZnO) _m (m is 0 or a natural number).

In addition, an In—Sn—Ga—Zn—O-based oxide that is an oxide of a quaternary metal or an In—Ga—Zn—O-based oxide that is an oxide of a ternary metal ( IGZO)), In-Al-Zn-O-based oxide, Sn-Ga-Zn-O-based oxide, Al-Ga-Zn-O-based oxide, Sn-Al-Zn-O-based oxide In-Zn-O-based oxides, Sn-Zn-O-based oxides, Al-Zn-O-based oxides, Zn-Mg-O-based oxides, Sn-Mg oxides that are binary metal oxides The same applies to the case where an —O-based oxide, an In—Mg—O-based oxide, an In—Ga—O-based oxide, or the like is used.

For example, FIG. 16A illustrates a model diagram of one group included in an In—Ga—Zn—O-based layer structure.

In FIG. 16A, the group constituting the In—Ga—Zn—O-based layer structure includes four tetracoordinate O atoms in the upper half and the lower half in order from the top. Is bonded to a Zn atom in the upper half, and through the three tetracoordinate O atoms in the lower half of the Zn atom, one tetracoordinate O atom exists in the upper half and the lower half one by one. It is bonded to Ga atoms, and through four tetracoordinate O atoms in the lower half of the Ga atoms, three tetracoordinate O atoms are bonded to In atoms in the upper half and the lower half. is there. A plurality of these groups are combined to form a unit.

FIG. 16B shows a unit composed of three groups. Note that FIG. 16C illustrates an atomic arrangement in the case where the layered structure in FIG. 16B is observed from the c-axis direction.

Here, charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are +3, +2, and +3, respectively. The included subunit has zero charge. For this reason, in the case of a combination of these subunits, the total charge of the group is always zero.

In addition, a group included in the In—Ga—Zn—O-based layer structure is not limited to the group illustrated in FIG. 16A, and a unit in which groups having different arrangements of In, Ga, and Zn are combined can be used. .

  Next, as illustrated in FIG. 12A, a conductive film 719 in contact with the gate electrode 707 and in contact with the oxide semiconductor layer 716 and a conductive film 720 in contact with the conductive film 708 and in contact with the oxide semiconductor layer 716 are formed. Form. The conductive films 719 and 720 function as a source electrode or a drain electrode.

  Specifically, the conductive film 719 and the conductive film 720 are formed by sputtering or vacuum deposition so as to cover the gate electrode 707 and the conductive film 708, and then processed (patterning) into a predetermined shape. By doing so, it can be formed.

  The conductive film to be the conductive films 719 and 720 is an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing any of the above elements as a component, or an alloy that combines the above elements. Examples include membranes. Alternatively, a high melting point metal film such as chromium, tantalum, titanium, molybdenum, or tungsten may be stacked below or above the metal film such as aluminum or copper. Aluminum or copper is preferably used in combination with a refractory metal material in order to avoid problems of heat resistance and corrosion. As the refractory metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, yttrium, or the like can be used.

  The conductive film to be the conductive films 719 and 720 may have a single-layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a titanium film, an aluminum film laminated on the titanium film, and a titanium film formed on the titanium film. Examples include a three-layer structure. Further, Cu—Mg—Al alloy, Mo—Ti alloy, Ti, and Mo have high adhesion to the oxide film. Therefore, a conductive film composed of Cu—Mg—Al alloy, Mo—Ti alloy, Ti, or Mo is stacked as a lower layer, and a conductive film composed of Cu is stacked as an upper layer. By using the conductive film 720, the adhesion between the insulating film which is an oxide film and the conductive films 719 and 720 can be increased.

  Alternatively, the conductive film to be the conductive films 719 and 720 may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide, tin oxide, zinc oxide, indium tin oxide, indium zinc oxide, or a metal oxide material containing silicon or silicon oxide can be used.

  In the case where heat treatment is performed after formation of the conductive film, the conductive film preferably has heat resistance enough to withstand the heat treatment.

  Note that each material and etching conditions are adjusted as appropriate so that the oxide semiconductor layer 716 is not removed as much as possible when the conductive film is etched. Depending on the etching conditions, a part of the exposed portion of the oxide semiconductor layer 716 may be etched to form a groove (a depressed portion).

In this embodiment, a titanium film is used for the conductive film. Therefore, the conductive film can be selectively wet-etched using a solution containing ammonia and aqueous hydrogen peroxide (ammonia hydrogen peroxide). Specifically, ammonia perwater obtained by mixing 31% by weight of hydrogen peroxide water, 28% by weight of ammonia water and water at a volume ratio of 5: 2: 2. Alternatively, the conductive film may be dry-etched using a gas containing chlorine (Cl ₂ ), boron chloride (BCl ₃ ), or the like.

  Note that in order to reduce the number of photomasks used in the photolithography process and the number of processes, the etching process may be performed using a resist mask formed by a multi-tone mask that gives multi-level intensity to transmitted light. A resist mask formed using a multi-tone mask has a shape with a plurality of thicknesses, and the shape can be further deformed by etching. Therefore, the resist mask can be used for a plurality of etching processes for processing into different patterns. . Therefore, a resist mask corresponding to at least two kinds of different patterns can be formed by using one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can be reduced, so that the process can be simplified.

  Further, an oxide conductive film functioning as a source region and a drain region may be provided between the oxide semiconductor layer 716 and the conductive films 719 and 720 functioning as a source electrode and a drain electrode. As a material for the oxide conductive film, a material containing zinc oxide as a component is preferable, and a material not containing indium oxide is preferable. As such an oxide conductive film, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, or the like can be used.

  For example, in the case of forming an oxide conductive film, patterning for forming the oxide conductive film and patterning for forming the conductive films 719 and 720 may be performed in a lump.

  By providing the oxide conductive film functioning as the source region and the drain region, the resistance between the oxide semiconductor layer 716, the conductive film 719, and the conductive film 720 can be reduced; thus, high-speed operation of the transistor can be realized. it can. Further, by providing the oxide conductive film functioning as a source region and a drain region, the withstand voltage of the transistor can be increased.

Next, plasma treatment using a gas such as N ₂ O, N ₂ , or Ar may be performed. Water or the like attached to the surface of the oxide semiconductor layer exposed by this plasma treatment is removed. Further, plasma treatment may be performed using a mixed gas of oxygen and argon.

  Note that after the plasma treatment, a gate insulating film 721 is formed so as to cover the conductive films 719 and 720 and the oxide semiconductor layer 716 as illustrated in FIG. Then, over the gate insulating film 721, the gate electrode 722 is formed in a position overlapping with the oxide semiconductor layer 716, and the conductive film 723 is formed in a position overlapping with the conductive film 719.

  The gate insulating film 721 can be formed using a material similar to that of the gate insulating film 703 and a similar stacked structure. Note that the gate insulating film 721 preferably contains as little moisture and impurities as hydrogen, and may be a single-layer insulating film or a plurality of stacked insulating films. When hydrogen is contained in the gate insulating film 721, the hydrogen penetrates into the oxide semiconductor layer 716, or hydrogen extracts oxygen in the oxide semiconductor layer 716, so that the resistance of the oxide semiconductor layer 716 is reduced (n-type reduction). And a parasitic channel may be formed. Therefore, it is important not to use hydrogen in the deposition method so that the gate insulating film 721 contains as little hydrogen as possible. It is preferable to use a material having a high barrier property for the gate insulating film 721. For example, as the insulating film having a high barrier property, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like can be used. In the case of using a plurality of stacked insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film having a low nitrogen content is placed closer to the oxide semiconductor layer 716 than the insulating film having a high barrier property. Form. Then, an insulating film with a high barrier property is formed so as to overlap with the conductive films 719, 720, and 716, with an insulating film having a low nitrogen content interposed therebetween. By using an insulating film having a high barrier property, impurities such as moisture or hydrogen are present in the oxide semiconductor layer 716, the gate insulating film 721, or the interface between the oxide semiconductor layer 716 and another insulating film and the vicinity thereof. It can be prevented from entering. Further, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film having a low nitrogen ratio so as to be in contact with the oxide semiconductor layer 716, the insulating film using a material having a high barrier property can be directly formed 716 can be prevented from touching.

  In this embodiment, the gate insulating film 721 having a structure in which a silicon nitride film having a thickness of 100 nm formed by a sputtering method is stacked over a silicon oxide film having a thickness of 200 nm formed by a sputtering method is formed. . The substrate temperature at the time of film formation may be from room temperature to 300 ° C., and is 100 ° C. in this embodiment.

  Note that heat treatment may be performed after the gate insulating film 721 is formed. The heat treatment is preferably performed at 200 ° C. to 400 ° C., for example, 250 ° C. to 350 ° C. in an atmosphere of nitrogen, ultra-dry air, or a rare gas (such as argon or helium). The gas preferably has a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less. In this embodiment, for example, heat treatment is performed at 250 ° C. for one hour in a nitrogen atmosphere. Alternatively, before the conductive film 719 and the conductive film 720 are formed, high-temperature and short-time RTA treatment may be performed as in the previous heat treatment performed on the oxide semiconductor layer for reducing moisture or hydrogen. good. By the heat treatment performed after the gate insulating film 721 containing oxygen is provided, oxygen vacancies are generated in the oxide semiconductor layer 716 due to the previous heat treatment performed on the oxide semiconductor layer 716. Even so, oxygen is supplied from the gate insulating film 721 to the oxide semiconductor layer 716. When oxygen is supplied to the oxide semiconductor layer 716, oxygen vacancies serving as donors in the oxide semiconductor layer 716 can be reduced and the stoichiometric composition ratio can be satisfied. The oxide semiconductor layer 716 preferably contains oxygen in an amount exceeding the stoichiometric composition ratio. As a result, the oxide semiconductor layer 716 can be made to be i-type, variation in electric characteristics of the transistor due to oxygen vacancies can be reduced, and electric characteristics can be improved. The timing of performing this heat treatment is not particularly limited as long as it is after the formation of the gate insulating film 721. Other processes, for example, heat treatment at the time of forming the resin film, and heat treatment for reducing the resistance of the transparent conductive film, By also serving, the oxide semiconductor layer 716 can be made to be i-type without increasing the number of steps.

  Further, oxygen vacancies serving as donors in the oxide semiconductor layer 716 may be reduced by performing heat treatment on the oxide semiconductor layer 716 in an oxygen atmosphere so that oxygen is added to the oxide semiconductor. The temperature of the heat treatment is, for example, 100 ° C. or higher and lower than 350 ° C., preferably 150 ° C. or higher and lower than 250 ° C. The oxygen gas used for the heat treatment under the oxygen atmosphere preferably does not contain water, hydrogen, or the like. Alternatively, the purity of the oxygen gas introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration in oxygen is 1 ppm or less, preferably 0.1 ppm). Or less).

  Alternatively, oxygen vacancies serving as donors may be reduced by adding oxygen to the oxide semiconductor layer 716 by an ion implantation method, an ion doping method, or the like. For example, oxygen converted into plasma with a microwave of 2.45 GHz may be added to the oxide semiconductor layer 716.

  The gate electrode 722 and the conductive film 723 can be formed by forming a conductive film over the gate insulating film 721 and then patterning the conductive film. The gate electrode 722 and the conductive film 723 can be formed using a material similar to that of the gate electrode 707 or the conductive films 719 and 720.

  The thicknesses of the gate electrode 722 and the conductive film 723 are 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, after a 150 nm gate electrode conductive film is formed by sputtering using a tungsten target, the conductive film is processed (patterned) into a desired shape by etching, whereby the gate electrode 722 and the conductive film are formed. A film 723 is formed. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by an ink-jet method, a manufacturing cost can be reduced because a photomask is not used.

  Through the above steps, the first transistor 111 is formed.

  Note that a portion where the conductive film 719 and the conductive film 723 overlap with the gate insulating film 721 provided therebetween corresponds to the first capacitor 113.

  Although the first transistor 111 is described using a single-gate transistor, a dual-gate structure including a plurality of channel formation regions by including a plurality of electrically connected gate electrodes as necessary. Alternatively, a multi-gate transistor can be formed.

  Note that for the insulating film in contact with the oxide semiconductor layer 716 (in this embodiment, the gate insulating film 721 corresponds), an insulating material containing a Group 13 element and oxygen may be used. Many oxide semiconductor materials contain a Group 13 element, and an insulating material containing a Group 13 element has good compatibility with an oxide semiconductor. By using this for an insulating film in contact with the oxide semiconductor layer, oxidation can be performed. The state of the interface with the physical semiconductor layer can be kept good.

  An insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of the insulating material containing a Group 13 element include gallium oxide, aluminum oxide, aluminum gallium oxide, and gallium aluminum oxide. Here, aluminum gallium oxide indicates that the aluminum content (atomic%) is higher than gallium content (atomic%), and gallium aluminum oxide means that the gallium aluminum content (atomic%) contains aluminum. The amount (atomic%) or more is shown.

  For example, when an insulating film is formed in contact with an oxide semiconductor layer containing gallium, the interface characteristics between the oxide semiconductor layer and the insulating film can be kept favorable by using a material containing gallium oxide for the insulating film. . For example, when an oxide semiconductor layer and an insulating film containing gallium oxide are provided in contact with each other, pileup of hydrogen at the interface between the oxide semiconductor layer and the insulating film can be reduced. Note that a similar effect can be obtained when an element of the same group as a constituent element of the oxide semiconductor is used for the insulating film. For example, it is also effective to form an insulating film using a material containing aluminum oxide. Note that aluminum oxide has a characteristic that water is difficult to permeate, and thus the use of the material is preferable in terms of preventing water from entering the oxide semiconductor layer.

  The insulating film in contact with the oxide semiconductor layer 716 is preferably made to have a state in which the amount of oxygen in the insulating material is higher than that in the stoichiometric composition ratio by heat treatment in an oxygen atmosphere, oxygen doping, or the like. Oxygen doping means adding oxygen to the bulk. The term “bulk” is used for the purpose of clarifying that oxygen is added not only to the surface of the thin film but also to the inside of the thin film. The oxygen dope includes oxygen plasma dope in which plasma oxygen is added to the bulk. Further, oxygen doping may be performed using an ion implantation method or an ion doping method.

For example, in the case where gallium oxide is used as the insulating film in contact with the oxide semiconductor layer 716, the composition of gallium oxide is changed to Ga ₂ O _X (X = 3 + α, 0 <α by performing heat treatment in an oxygen atmosphere or oxygen doping. <1).

In the case where aluminum oxide is used as the insulating film in contact with the oxide semiconductor layer 716, the composition of the aluminum oxide is changed to Al ₂ O _X (X = 3 + α, 0 <α by performing heat treatment in an oxygen atmosphere or oxygen doping. <1).

In the case where gallium aluminum oxide (aluminum gallium oxide) is used as the insulating film in contact with the oxide semiconductor layer 716, the composition of gallium aluminum oxide (aluminum gallium oxide) is changed by performing heat treatment in an oxygen atmosphere or oxygen doping. _{Ga X Al 2-X O 3} + α (0 <X <2,0 <α <1) can be.

  By performing the oxygen doping treatment, an insulating film having a region where oxygen is higher than the stoichiometric composition ratio can be formed. When the insulating film including such a region is in contact with the oxide semiconductor layer, excess oxygen in the insulating film is supplied to the oxide semiconductor layer, and the oxide semiconductor layer or the interface between the oxide semiconductor layer and the insulating film is supplied. The number of oxygen defects can be reduced, and the oxide semiconductor layer can be made i-type or i-type as close as possible.

An oxide semiconductor layer in which oxygen defects are reduced by supplying excess oxygen in the insulating film to the oxide semiconductor layer is highly purified by sufficiently reducing the hydrogen concentration, and by supplying sufficient oxygen. An oxide semiconductor layer in which defect levels in an energy gap due to oxygen vacancies are reduced can be obtained. Therefore, an oxide semiconductor layer with extremely low carrier concentration can be obtained, and a transistor with extremely low off-state current can be obtained. By applying such a transistor with extremely low off-state current to the first transistor in the above embodiment, the transistor can be regarded as an insulator when it is turned off. Therefore, by using it for the first transistor, a decrease in the potential held in the storage node D_HOLD can be suppressed to an extremely small level. As a result, even when the supply of power supply voltage is stopped, a change in potential of the storage node D_HOLD can be reduced, and a nonvolatile storage device that can prevent the loss of stored data can be obtained.

  Note that the insulating film having a region containing more oxygen than the stoichiometric composition ratio is one of the insulating film located in the upper layer and the insulating film located in the lower layer among the insulating films in contact with the oxide semiconductor layer 716. However, it is preferable to use it for both insulating films. An insulating film having a region containing more oxygen than the stoichiometric composition ratio is used as an insulating film located above and below the insulating film in contact with the oxide semiconductor layer 716 so that the oxide semiconductor layer 716 is interposed therebetween. Thus, the above effect can be further enhanced.

The insulating film used for the upper layer or the lower layer of the oxide semiconductor layer 716 may be an insulating film having the same constituent element in the upper layer and the lower layer, or may be an insulating film having different constituent elements. For example, the upper layer and the lower layer may be gallium oxide having a composition of Ga ₂ O _X (X = 3 + α, 0 <α <1), and one of the upper layer and the lower layer may have a composition of Ga ₂ O _X (X = 3 + α, 0 <Α <1) may be gallium oxide, and the other may be aluminum oxide having a composition of Al ₂ O _X (X = 3 + α, 0 <α <1).

The insulating film in contact with the oxide semiconductor layer 716 may be a stack of insulating films having a region where oxygen is higher than the stoichiometric composition ratio. For example, gallium oxide having a composition of Ga ₂ O _X (X = 3 + α, 0 <α <1) is formed over the oxide semiconductor layer 716, and the composition of the gallium oxide is Ga _X Al _{2 -X} O _{3 + α} (0 < You may form the gallium aluminum oxide (aluminum gallium oxide) of X <2, 0 <α <1). Note that the lower layer of the oxide semiconductor layer 716 may be a stack of insulating films having a region with more oxygen than the stoichiometric composition ratio, and both the upper layer and the lower layer of the oxide semiconductor layer 716 may be stoichiometric. An insulating film having a region where oxygen is higher than the composition ratio may be stacked.

  Next, as illustrated in FIG. 12C, an insulating film 724 is formed so as to cover the gate insulating film 721, the conductive film 723, and the gate electrode 722. The insulating film 724 can be formed by a PVD method, a CVD method, or the like. Alternatively, the insulating layer can be formed using a material including an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, or aluminum oxide. Note that the insulating film 724 is preferably formed using a material with a low dielectric constant or a structure with a low dielectric constant (such as a porous structure). This is because by reducing the dielectric constant of the insulating film 724, parasitic capacitance generated between wirings and electrodes can be reduced, and operation speed can be increased. Note that although the insulating film 724 has a single-layer structure in this embodiment, one embodiment of the present invention is not limited to this, and a stacked structure of two or more layers may be used.

  Next, an opening 725 is formed in the gate insulating film 721 and the insulating film 724 so that part of the conductive film 720 is exposed. After that, a wiring 726 that is in contact with the conductive film 720 in the opening 725 is formed over the insulating film 724.

  The wiring 726 is formed by forming a conductive film using a PVD method or a CVD method and then patterning the conductive film. As a material for the conductive film, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing the above-described element as a component, or the like can be used. Any of manganese, magnesium, zirconium, beryllium, neodymium, scandium, or a combination of these may be used.

  More specifically, for example, a method in which a titanium film is thinly formed (about 5 nm) by a PVD method in a region including an opening of the insulating film 724 and then an aluminum film is formed so as to be embedded in the opening 725 is applied. it can. Here, the titanium film formed by the PVD method has a function of reducing an oxide film (natural oxide film or the like) on the surface to be formed and reducing contact resistance with the lower electrode or the like (here, the conductive film 720). Further, hillocks of the aluminum film can be prevented. Further, after forming a barrier film made of titanium, titanium nitride, or the like, a copper film may be formed by a plating method.

  The opening 725 formed in the insulating film 724 is preferably formed in a region overlapping with the conductive film 708. By forming the opening 725 in such a region, an increase in element area due to the contact region can be suppressed.

  Here, the case where the connection between the impurity region 704 and the conductive film 720 and the connection between the conductive film 720 and the wiring 726 are overlapped without using the conductive film 708 is described. In this case, an opening (referred to as a lower opening) is formed in the insulating film 712 and the insulating film 713 formed over the impurity region 704, a conductive film 720 is formed so as to cover the lower opening, and then the gate is formed. In the insulating film 721 and the insulating film 724, an opening (referred to as an upper opening) is formed in a region overlapping with the lower opening, and the wiring 726 is formed. When the upper opening is formed in a region overlapping with the lower opening, the conductive film 720 formed in the lower opening may be disconnected by etching. In order to avoid this, if the lower opening and the upper opening are formed so as not to overlap, there is a problem that the element area increases.

  As shown in this embodiment mode, by using the conductive film 708, an upper opening can be formed without disconnecting the conductive film 720. Accordingly, since the lower opening and the upper opening can be provided so as to overlap with each other, an increase in element area due to the opening can be suppressed. That is, the degree of integration of the semiconductor device can be increased.

  Next, an insulating film 727 is formed so as to cover the wiring 726. A semiconductor memory device can be manufactured through the series of steps described above.

  Note that in the above manufacturing method, the conductive films 719 and 720 functioning as a source electrode and a drain electrode are formed after the oxide semiconductor layer 716. Thus, as illustrated in FIG. 12B, in the first transistor 111 obtained by the above manufacturing method, a conductive film 719 and a conductive film 720 are formed over the oxide semiconductor layer 716. However, in the first transistor 111, a conductive film functioning as a source electrode and a drain electrode is provided below the oxide semiconductor layer 716, that is, between the oxide semiconductor layer 716, the insulating film 712, and the insulating film 713. May be.

  13A and 13B, the conductive film 719 and the conductive film 720 functioning as a source electrode and a drain electrode are provided between the oxide semiconductor layer 716, the insulating film 712, and the insulating film 713. A cross-sectional view is shown. The first transistor 111 illustrated in FIG. 13 can be obtained by forming the conductive film 719 and the conductive film 720 after forming the insulating film 713 and then forming the oxide semiconductor layer 716.

Incidentally, a magnetic tunnel junction element (MTJ element) is known as a transistor used in a nonvolatile semiconductor memory device. The MTJ element is an element that stores information by being in a low resistance state if the spin directions in the films arranged above and below the insulating film are parallel and in a high resistance state if the spin directions are antiparallel. Therefore, the principle is completely different from that of the semiconductor memory device including the oxide semiconductor described in this embodiment. Table 1 shows a comparison between the MTJ element and the semiconductor memory device according to the present embodiment.

Since the MTJ element uses a magnetic material, there is a drawback that the magnetism is lost when the temperature is higher than the Curie temperature. Further, since the MTJ element is current driven, it is compatible with a silicon bipolar device, but the bipolar device is not suitable for integration. The MTJ element has a problem that although the write current is very small, the power consumption increases due to the increase in memory capacity.

In principle, the MTJ element is weak in magnetic field resistance, and when exposed to a strong magnetic field, the direction of spin tends to go wrong. In addition, it is necessary to control the magnetization fluctuation caused by the nanoscale formation of the magnetic material used in the MTJ element.

Furthermore, since the MTJ element uses a rare earth element, it requires considerable care to incorporate it into a silicon semiconductor process that dislikes metal contamination. The MTJ element is considered to be expensive in view of the material cost per bit.

On the other hand, the semiconductor memory device using an oxide semiconductor described in this embodiment has the same element structure and operation principle as those of a silicon MOSFET except that a semiconductor material forming a channel is a metal oxide. A semiconductor memory device using an oxide semiconductor is not affected by a magnetic field and has a characteristic that a soft error cannot occur. Therefore, it can be said that the compatibility with the silicon integrated circuit is very good.

  This embodiment can be implemented in combination with any of the above embodiments as appropriate.

100 Semiconductor memory device 101 Memory circuit 102 Second capacitor element 103 Charge storage circuit 104 Data detection circuit 105 Timing control circuit 106 Inverter circuit 111 First transistor 112 Second transistor 113 First capacitor element 114 Third transistor 115 Fourth transistor 116 NAND circuit 117 OR circuit 150 signal processing device 151 arithmetic device 152 arithmetic device 153 semiconductor memory device 154 semiconductor memory device 155 semiconductor memory device 156 control device 157 power supply control circuit 201 delay circuit portion 202 buffer circuit portion 203 resistance element 204 capacitive element 205 n-channel transistor 206 p-channel transistor 401 inverter circuit 402 semiconductor memory device 403 semiconductor memory device group 404 delayed high power supply potential generation circuit 700 701 Insulating film 702 Semiconductor film 703 Gate insulating film 704 Impurity region 705 Mask 706 Opening 707 Gate electrode 708 Conductive film 709 Impurity region 710 Channel formation region 711 Impurity region 712 Insulating film 713 Insulating film 716 Oxide semiconductor layer 719 Conductive film 720 Conductive Film 721 gate insulating film 722 gate electrode 723 conductive film 724 insulating film 725 opening 726 wiring 727 insulating film 9900 substrate 9901 ALU
9902 ALU Controller
9903 Instruction Decoder
9904 Interrupt Controller
9905 Timing Controller
9906 Register
9907 Register Controller
9908 Bus I / F
9909 ROM
9920 ROM ・ I / F

Claims (6)

A memory circuit including a first transistor including an oxide semiconductor in a semiconductor layer, a first capacitor, and a second transistor;
A first terminal of the first transistor is electrically connected to a data input line;
A gate of the first transistor is electrically connected to a clock signal line;
A second terminal of the first transistor is electrically connected to a first electrode of the first capacitor;
A second terminal of the first transistor is electrically connected to a gate of the second transistor;
A second capacitive element for accumulating charges for reading data held in the memory circuit;
A charge storage circuit electrically connected to a power supply potential line and controlling charge storage in the second capacitor element;
A data detection circuit that controls conduction or non-conduction between the first electrode of the second capacitor and the first terminal of the second transistor;
A timing control circuit;
An inverter circuit that inverts and outputs the potential of the first electrode of the second capacitive element,
In the first period in which the clock signal is supplied to the clock signal line, the timing control circuit causes the charge storage circuit and the data detection circuit to be alternately turned on according to the toggle operation of the clock signal. In the second period immediately after the power supply voltage is supplied to the power supply potential line, the charge storage circuit generates the power storage voltage signal and a signal obtained by delaying the power supply voltage signal. Generating a signal for controlling charge accumulation in the second capacitor element ;
The first transistor is a semiconductor memory device positioned on the second transistor . A memory circuit including a first transistor including an oxide semiconductor in a semiconductor layer, a first capacitor, and a second transistor;
A first terminal of the first transistor is electrically connected to a data input line;
A gate of the first transistor is electrically connected to a clock signal line;
A second terminal of the first transistor is electrically connected to a first electrode of the first capacitor;
A second terminal of the first transistor is electrically connected to a gate of the second transistor;
A second capacitive element for accumulating charges for reading data held in the memory circuit;
A third transistor having a first terminal electrically connected to a power supply potential line and a second terminal electrically connected to a first electrode of the second capacitor;
A fourth transistor having a first terminal electrically connected to the first electrode of the second capacitor, and a second terminal electrically connected to the first terminal of the second transistor;
A timing control circuit;
An inverter circuit that inverts and outputs the potential of the first electrode of the second capacitive element,
In the first period in which the clock signal is supplied to the clock signal line, the timing control circuit is configured such that the third transistor and the fourth transistor are alternately turned on according to the toggle operation of the clock signal. In the second period immediately after the power supply voltage is supplied to the power supply potential line, the power supply voltage signal and the signal obtained by delaying the power supply voltage signal are used in the second period. Generate a signal to turn on the transistor ,
The first transistor is a semiconductor memory device positioned on the second transistor . In claim 1,
The data detection circuit is a circuit that converts the potential of the first electrode of the second capacitive element into a signal in which the data is inverted, depending on whether or not the charge accumulated in the second capacitive element is released. Semiconductor memory device. In any one of Claim 1 thru | or 3,
The semiconductor memory device, wherein the second transistor includes silicon in a semiconductor layer. In any one of Claims 1 thru | or 4 ,
The circuit for delaying the signal of the power supply voltage is a semiconductor memory device having a delay circuit and a buffer circuit. In any one of Claims 1 thru | or 5 ,
The timing control circuit receives a negative logical product circuit to which the power supply voltage signal and a signal obtained by delaying the power supply voltage signal are input, and an output signal of the negative logical product circuit and the clock signal. A semiconductor memory device having an OR circuit.