JPH07220493A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device in which power consumption is reduced. CONSTITUTION:The semiconductor device comprises a circuit 21 for detecting matching between an address signal inputted during current cycle and an address signal inputted during previous cycle, a ROM 11a for reading out a data based on the address signal of current cycle when mismatch is detected by the circuit 21 and stopping the reading operation when matching is detected, and a register 12a for holding the data outputted from the ROM 11a during current cycle upon detection of mismatch and holding the data outputted from the ROM 11a during previous cycle continuously upon detection of matching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a dynamic device for precharging and reading data.

[0002]

2. Description of the Related Art ROM (Read Only M
There is a circuit shown in FIG. 6 as a circuit for reading the data written in the emory). The waveform of each signal in this circuit is shown in FIG.

A clock signal and an address signal A are input to the ROM 11. Precharge is started in the ROM 11 by the rising edge of the clock signal, and precharge is completed in the first half cycle of this clock signal.

Thereafter, in the latter half cycle of the clock signal, the data D corresponding to the address signal A is read from the ROM 11.
Is output. For example, if the address signal A2 is ROM
When input to 11, the data D2 is output.

The data D output from the ROM 11 is input to the instruction register IR12. The instruction register IR12 holds the data D at the rising edge of the clock signal. Data held D
In the next cycle, the instruction register 12
Output to the outside.

Further, as another circuit for reading data by the precharge method, as shown in FIG.
Some have 1 and register 43. The waveforms of the clock signal, the data signal D, the output data O of the adder 41, and the output data O of the register 43 in this case are as shown in FIG.

The clock signal and the data D to be added are input to the adder 41. Precharge is performed in the first half cycle of the clock signal in synchronization with the rising edge of the clock signal. The adder 41 performs addition in the latter half cycle of the clock signal, and the result is data O
Output as. The data O is held in the register 43 and output to the outside in the next cycle.

[0008]

However, the conventional semiconductor device has the following problems.

In the circuit shown in FIG. 6, even when the same address signal A2 is continuously input to the ROM 11 in the first cycle and the second cycle as shown in the time chart of FIG. Pre-charges each cycle and reads and outputs the same data D2.

Similarly, in the circuit shown in FIG. 8, even when the same data D2 is input to the adder 41, precharging is performed each time and the same addition result O2 is output.

As described above, conventionally, even when the same address or data is input and the same result is output, the precharge is repeated each time and power is wasted. This problem has become remarkable as the circuit becomes larger and larger year by year.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device capable of reducing power consumption.

[0013]

The semiconductor device of the present invention comprises:
A semiconductor device which receives a signal periodically from the outside, performs a precharge operation to generate and outputs data corresponding to the signal, and receives the signal from the outside periodically.
A signal match detection circuit that detects a match between two consecutive signals, and when the signal match detection circuit detects a mismatch, generates and outputs data corresponding to the signal, and the signal match detection circuit detects a match. In this case, a data output unit for maintaining the precharge operation and stopping the operation of generating data is provided.

[0014]

When the signal coincidence detection circuit receives a signal periodically and detects that two consecutive signals do not coincide with each other, the data output section generates and outputs data corresponding to this signal, and outputs the signal coincidence. When the detection circuit detects the coincidence, the precharge operation is maintained and the operation of generating data is stopped, so that the power consumption is reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a semiconductor device according to the first embodiment of the present invention, and the waveform of each signal is shown in the time chart of FIG. Unlike the conventional device shown in FIG. 6, an address coincidence detection circuit 21 is newly provided, and the ROM 1
Reference numeral 1a includes a precharge control circuit that controls the precharge operation according to the detection signal output from the address coincidence detection circuit 21. In addition, instruction register 1
Reference numeral 2a is a master-slave type which is composed of an input enable flip-flop and which is synchronized with a clock signal.

The address coincidence detection circuit 21 has a D flip-flop 22 and an EX-NOR gate 23.
The address signal Ai (i is an integer) is input to the data terminal D of the D flip-flop 22, and the clock signal is input to the clock terminal CK. The address signal Ai changes in synchronization with the rising edge of the clock signal, after being delayed by the delay time.

The address signal Ai is input to the data terminal D of the D flip-flop 22, and the clock signal is input to the clock terminal CK. In synchronization with the rising edge of the next cycle of this clock signal, the D flip-flop 2
The address signal Ai is output from 2 and input to one input terminal of the EX-NOR gate 23. The other input terminal of the EX-NOR gate receives the next address signal Ai + 1 in synchronization with the rising edge of the current cycle of this clock signal.
Has been entered. The EX-NOR gate 23 compares the current address signal Ai + 1 with the address signal Ai one cycle before, and outputs a detection signal of logic "0" to the ROM 11a when they do not match, and when they match. A detection signal of logic "1" is output.

The clock signal, the current address signal Ai + 1, and the detection signal output from the address coincidence detection circuit 21 are input to the ROM 11a. In the ROM 11a, precharge is performed in the first half cycle in which the clock signal is at the high level.

1 in the latter half when the clock signal goes low
In the / 2 cycle, when the detection signal is logic "1", that is, when the current address signal Ai + 1 and the address signal Ai one cycle before do not match, the precharge ends and the current address is The data Di + 1 stored in the cell indicated by the signal Ai + 1 is output. When the detection signal is logic "1", that is, when the current address signal Ai + 1 matches the address signal Ai one cycle before, the read operation is stopped and the current precharge operation is maintained. The output level of the ROM 11a at this time is fixed to either the logic "1" or "0" level.

The output data Di + 1 is output to the instruction register 12a. The instruction register 12a has a clock signal and a ROM 11a.
The data Di + 1 output from the address match detection circuit 21 and the detection signal output from the address match detection circuit 21 are input. The detect signal acts as an input enable signal. That is, when the detection signal is logic "0" and indicates an address disagreement, RO11 is synchronized with the rising edge of the clock signal in the next cycle.
Data Di + 1 output from a is input, and this data D
i + 1 is held during this cycle and output to the outside. On the contrary, when the detection signal is the logic "1" and indicates the coincidence of the address signals, even if the clock signal rises in the next cycle, the same data Di as in the previous cycle is held and its output is maintained.

For example, in the first cycle shown in FIG. 2, when the clock signal rises, the address signal changes from A1 to A2, and this address signal A2 is stored in the ROM 11
a and the address coincidence detection circuit 21. In the address match detection circuit 21, the first half of the clock signal 1 /
During the two cycles, the address signal A1 of the previous cycle and the current address signal A2 are compared, and because they do not match, a detection signal of logic "0" is output to the ROM 11a. R
In the OM 11a, the clock signal is precharged during the first half cycle.

In the latter half cycle of the clock signal, since the address signals do not match, the data D2 corresponding to the current address signal A2 is output from the ROM 11a. The data D2, the clock signal, and the detection signal are output to the instruction register 12a. The data D2 is fetched and held in the instruction register 12a, and the data D2 is output in synchronization with the rising edge of the clock signal in the next second cycle.

When the clock signal rises in the second cycle, the address signal changes. However, the address signal A2 in this cycle is the same as the address signal A2 in the first cycle. The address signal A2 of the second cycle and the address signal A2 of the first cycle are the address coincidence detection circuit 2
1 is detected and the detection signal of logic "1" indicating the match is RO
It is output to M11a and the instruction register 12a. Reading of data is stopped in the ROM 11a,
The precharge operation is maintained until the latter half cycle of the clock signal. Instruction register 12a
Holds the data D2 held in the second cycle and outputs it to the outside based on the detection signal of logic "1".

As described above, according to the present embodiment, when the address signals Ai continuously match over a plurality of cycles, the read operation is stopped without precharging for each cycle. Then, the data Di corresponding to the address signal Ai is held and output by the instruction register 12a, so that the power consumption can be reduced.

Here, the detection signal output from the address coincidence detection circuit 21 is applied to the ROM 11a, and as described above, the ROM 11a controls the precharge operation based on this detection signal. This precharge control circuit can be configured as shown in FIG. 3, for example. The clock signal and the detection signal are input to the OR gate 31.

In each cycle, the clock signal is at the high level in the first half cycle. Therefore,
The OR gate 31 outputs a precharge signal of logic "1" regardless of the level of the detection signal, and the precharge operation is performed.

In the latter half cycle, the clock signal becomes low level. The precharge signal during this period is determined by the level of the detection signal. Address signal Ai of the previous cycle and address signal A of the current cycle
When i + 1 does not match, a detection signal of logic "0" is input to the OR gate 31, and a precharge signal of logic "0" is output. As a result, the precharge operation is
It ends when there are two cycles.

On the contrary, when the address signal Ai of the previous cycle and the address signal Ai + 1 of the current cycle match, a detection signal of logic "1" is input to the OR gate 31, and precharge of logic "1" is performed. The signal is output. As a result,
The precharge signal becomes logic "1" and the precharge operation is continuously maintained in the latter half cycle.

The semiconductor device according to the second embodiment of the present invention includes an adder 41a and a register 4 as shown in FIG.
The data coincidence detection circuit 42 is newly added to 3a. The waveform of each signal in this case changes like the time chart shown in FIG.

In the second embodiment, the operation is similar to that of the first embodiment. That is, in the first half cycle of the clock signal, the data coincidence detection circuit 42 detects whether or not the data Di of the previous cycle and the data Di + 1 of the present cycle match. For example, second
The data D of the first cycle like the data D2 of the cycle
When it matches with 1, the detection signal of logic "1" is given to the adder 41a and the register 43a. When the data do not match, a detection signal of logic "0" is output. In the adder 41a, precharge is performed during the first half cycle of this clock signal.

When the data Di and Di + 1 do not match in the latter half cycle of the clock signal, precharge is completed in the adder 41a as in the conventional case, addition is performed, and the result is the data Oi. It is output as +1.
This data Oi + 1 is held in the register 43a in synchronization with the rising of the clock signal of the next cycle, and is output to the outside.

When the data match, a detection signal of logic "1" is given to the adder 41a to stop the addition operation,
Precharge operation is maintained. The register 43a receives the detection signal of logic "1", continuously holds the data Oi of the previous cycle, and outputs it to the outside.

As described above, when the data input from the outside is the same as in the previous cycle, the addition operation is stopped in the adder 41a and the precharge operation is maintained, so that the power consumption can be reduced.

The above-described embodiments are merely examples and do not limit the present invention. For example, the embodiment includes a ROM or an adder, but the present invention is not limited to this, and the present invention can be widely applied to a dynamic circuit that performs a precharge operation. When the signal input from the outside is continuously the same in a plurality of cycles, by applying the present invention, the precharge operation can be maintained and unnecessary power consumption can be reduced.

The precharge control circuit shown in FIG. 3 is also merely an example. That is, if the signals input from the outside are continuously matched in a plurality of cycles, any control can be performed so that the precharge operation is continuously maintained.

[0036]

As described above, according to the semiconductor device of the present invention, the precharge operation is maintained and the operation of generating data is stopped when the two consecutive input signals match. It is possible to reduce power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a time chart showing waveforms of signals in the semiconductor device.

FIG. 3 is a circuit diagram showing a configuration of a precharge control circuit in the semiconductor device.

FIG. 4 is a circuit diagram showing a configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a time chart showing waveforms of respective signals in the semiconductor device.

FIG. 6 is a circuit diagram showing a configuration of a conventional semiconductor device.

FIG. 7 is a time chart showing waveforms of signals in the semiconductor device.

FIG. 8 is a circuit diagram showing the configuration of another conventional semiconductor device.

FIG. 9 is a time chart showing waveforms of respective signals in the semiconductor device.

[Explanation of symbols]

 11a ROM 12a instruction register 21 address match detection circuit 22,43 D flip-flop 23,44 EX-NOR gate 31 OR gate 41a adder 42 data match detection circuit 43a register

Claims (3)

[Claims] 1. A semiconductor device which receives a signal periodically from the outside, performs a precharge operation to generate and outputs data corresponding to the signal, and in a semiconductor device to which the signal is applied periodically from the outside, A signal match detection circuit that detects a signal match, and when the signal match detection circuit detects a mismatch, generates and outputs data corresponding to the signal, and when the signal match detection circuit detects a match, a pre-match is generated. A semiconductor device, comprising: a data output unit that maintains a charge operation and stops an operation of generating data. 2. A semiconductor device which receives a clock signal and an address signal and reads and outputs data corresponding to the address signal, wherein the address signal input in the current cycle and the address signal input in the previous cycle An address match detection circuit that detects a match with an address signal, and when the address match detection circuit detects a mismatch, reads and outputs data based on the address signal of the current cycle, and the address match detection circuit detects a match. When the address match detection circuit detects a mismatch, the storage unit holds the data output from the storage unit in the current cycle, and the address match detection circuit detects a match. When the data is output, the data output from the storage unit in the previous cycle is retrieved. The semiconductor device is characterized in that a register for continued retention. 3. A clock signal and a data signal are input,
In a semiconductor device that performs a predetermined calculation using the data signal and outputs a calculation result, a data match detection circuit that detects a match between the data signal input in the current cycle and the data signal input in the previous cycle, When a mismatch is detected by the data match detection circuit, a predetermined operation is performed using the data signal of the current cycle, the operation result is output, and when the match is detected by the address match detection circuit, the operation operation is stopped. The operation unit holds the data output from the storage unit in the current cycle when a mismatch is detected by the data match detection circuit, and holds the data in the previous cycle when a match is detected by the data match detection circuit. A semiconductor device comprising: a register for continuously holding the calculation result output from the calculation unit.