JP5837339B2 - 半導体装置の製造方法及び半導体装置 - Google Patents

半導体装置の製造方法及び半導体装置 Download PDF

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Publication number
JP5837339B2
JP5837339B2 JP2011136474A JP2011136474A JP5837339B2 JP 5837339 B2 JP5837339 B2 JP 5837339B2 JP 2011136474 A JP2011136474 A JP 2011136474A JP 2011136474 A JP2011136474 A JP 2011136474A JP 5837339 B2 JP5837339 B2 JP 5837339B2
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Prior art keywords
solder
solder ball
semiconductor device
support plate
layer
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JP2011136474A
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Japanese (ja)
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JP2013004865A5 (https=
JP2013004865A (ja
Inventor
功一 田中
功一 田中
倉嶋　信幸
信幸 倉嶋
肇 飯塚
肇 飯塚
鉄也 小山
鉄也 小山
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2011136474A priority Critical patent/JP5837339B2/ja
Priority to US13/526,821 priority patent/US8736053B2/en
Publication of JP2013004865A publication Critical patent/JP2013004865A/ja
Publication of JP2013004865A5 publication Critical patent/JP2013004865A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2011136474A 2011-06-20 2011-06-20 半導体装置の製造方法及び半導体装置 Active JP5837339B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011136474A JP5837339B2 (ja) 2011-06-20 2011-06-20 半導体装置の製造方法及び半導体装置
US13/526,821 US8736053B2 (en) 2011-06-20 2012-06-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011136474A JP5837339B2 (ja) 2011-06-20 2011-06-20 半導体装置の製造方法及び半導体装置

Publications (3)

Publication Number Publication Date
JP2013004865A JP2013004865A (ja) 2013-01-07
JP2013004865A5 JP2013004865A5 (https=) 2014-07-24
JP5837339B2 true JP5837339B2 (ja) 2015-12-24

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JP2011136474A Active JP5837339B2 (ja) 2011-06-20 2011-06-20 半導体装置の製造方法及び半導体装置

Country Status (2)

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US (1) US8736053B2 (https=)
JP (1) JP5837339B2 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012114173A (ja) * 2010-11-23 2012-06-14 Shinko Electric Ind Co Ltd 半導体装置の製造方法及び半導体装置
US8928134B2 (en) 2012-12-28 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package bonding structure and method for forming the same
US9305853B2 (en) 2013-08-30 2016-04-05 Apple Inc. Ultra fine pitch PoP coreless package
US9613933B2 (en) 2014-03-05 2017-04-04 Intel Corporation Package structure to enhance yield of TMI interconnections
CN106030783B (zh) * 2014-03-27 2019-06-18 英特尔公司 用于低温附接的混合互连
US10236267B2 (en) * 2014-08-01 2019-03-19 Kyocera International, Inc. Methods of forming flip chip systems
JP6319026B2 (ja) * 2014-09-29 2018-05-09 日亜化学工業株式会社 発光装置及びその製造方法
US10231338B2 (en) 2015-06-24 2019-03-12 Intel Corporation Methods of forming trenches in packages structures and structures formed thereby
KR102420126B1 (ko) 2016-02-01 2022-07-12 삼성전자주식회사 반도체 소자
TWI602275B (zh) * 2016-10-14 2017-10-11 恆勁科技股份有限公司 封裝結構及其製作方法
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541153B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
CN116403973B (zh) * 2023-04-23 2025-01-17 长鑫存储技术有限公司 封装叠层结构及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
JP4831502B2 (ja) * 2008-09-25 2011-12-07 日立金属株式会社 耐落下衝撃特性に優れた接続端子用ボールおよび接続端子ならびに電子部品
JP5214554B2 (ja) * 2009-07-30 2013-06-19 ラピスセミコンダクタ株式会社 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法
KR20120109524A (ko) * 2009-11-27 2012-10-08 스미또모 베이크라이트 가부시키가이샤 전자 장치의 제조 방법, 전자 장치, 전자 장치 패키지의 제조 방법, 전자 장치 패키지

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JP2013004865A (ja) 2013-01-07
US8736053B2 (en) 2014-05-27
US20120319274A1 (en) 2012-12-20

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