JP5835696B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP5835696B2
JP5835696B2 JP2012195167A JP2012195167A JP5835696B2 JP 5835696 B2 JP5835696 B2 JP 5835696B2 JP 2012195167 A JP2012195167 A JP 2012195167A JP 2012195167 A JP2012195167 A JP 2012195167A JP 5835696 B2 JP5835696 B2 JP 5835696B2
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Japan
Prior art keywords
layer
wiring
contact
taper
contact hole
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Expired - Fee Related
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JP2012195167A
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English (en)
Japanese (ja)
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JP2014053369A (ja
JP2014053369A5 (https=
Inventor
葉 芽 里 稲
葉 芽 里 稲
沢 健 飛
沢 健 飛
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Toshiba Corp
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Toshiba Corp
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Publication date
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Priority to JP2012195167A priority Critical patent/JP5835696B2/ja
Priority to US13/836,215 priority patent/US9024443B2/en
Publication of JP2014053369A publication Critical patent/JP2014053369A/ja
Publication of JP2014053369A5 publication Critical patent/JP2014053369A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2012195167A 2012-09-05 2012-09-05 半導体装置およびその製造方法 Expired - Fee Related JP5835696B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012195167A JP5835696B2 (ja) 2012-09-05 2012-09-05 半導体装置およびその製造方法
US13/836,215 US9024443B2 (en) 2012-09-05 2013-03-15 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012195167A JP5835696B2 (ja) 2012-09-05 2012-09-05 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2014053369A JP2014053369A (ja) 2014-03-20
JP2014053369A5 JP2014053369A5 (https=) 2014-10-16
JP5835696B2 true JP5835696B2 (ja) 2015-12-24

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JP2012195167A Expired - Fee Related JP5835696B2 (ja) 2012-09-05 2012-09-05 半導体装置およびその製造方法

Country Status (2)

Country Link
US (1) US9024443B2 (https=)
JP (1) JP5835696B2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11183381B2 (en) 2019-03-15 2021-11-23 Kabushiki Kaisha Toshiba Semiconductor device

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US9583429B2 (en) 2013-11-14 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of forming same
US20150279793A1 (en) * 2014-03-27 2015-10-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9184060B1 (en) * 2014-11-14 2015-11-10 Lam Research Corporation Plated metal hard mask for vertical NAND hole etch
CN110246827B (zh) * 2014-12-16 2021-10-15 旺宏电子股份有限公司 半导体元件及其制造方法
US9449915B2 (en) * 2014-12-24 2016-09-20 Macronix International Co., Ltd. Semiconductor device and method of manufacturing the same
US9685555B2 (en) * 2014-12-29 2017-06-20 Stmicroelectronics, Inc. High-reliability, low-resistance contacts for nanoscale transistors
US9443921B2 (en) * 2015-02-10 2016-09-13 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
CN104766869B (zh) * 2015-04-07 2018-01-26 合肥鑫晟光电科技有限公司 阵列基板及其制备方法、显示装置
US10410883B2 (en) 2016-06-01 2019-09-10 Corning Incorporated Articles and methods of forming vias in substrates
US10794679B2 (en) 2016-06-29 2020-10-06 Corning Incorporated Method and system for measuring geometric parameters of through holes
US10134657B2 (en) 2016-06-29 2018-11-20 Corning Incorporated Inorganic wafer having through-holes attached to semiconductor wafer
CN106024636B (zh) * 2016-07-12 2023-08-04 杭州士兰集成电路有限公司 槽栅功率器件及制作方法
US11078112B2 (en) 2017-05-25 2021-08-03 Corning Incorporated Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same
US10580725B2 (en) 2017-05-25 2020-03-03 Corning Incorporated Articles having vias with geometry attributes and methods for fabricating the same
US12180108B2 (en) 2017-12-19 2024-12-31 Corning Incorporated Methods for etching vias in glass-based articles employing positive charge organic molecules
JP2019121685A (ja) * 2018-01-05 2019-07-22 東京エレクトロン株式会社 エッチング方法
US11554984B2 (en) 2018-02-22 2023-01-17 Corning Incorporated Alkali-free borosilicate glasses with low post-HF etch roughness
US11152294B2 (en) 2018-04-09 2021-10-19 Corning Incorporated Hermetic metallized via with improved reliability
US10847482B2 (en) 2018-05-16 2020-11-24 Micron Technology, Inc. Integrated circuit structures and methods of forming an opening in a material
US10651100B2 (en) 2018-05-16 2020-05-12 Micron Technology, Inc. Substrates, structures within a scribe-line area of a substrate, and methods of forming a conductive line of a redistribution layer of a substrate and of forming a structure within a scribe-line area of the substrate
WO2020061437A1 (en) 2018-09-20 2020-03-26 Industrial Technology Research Institute Copper metallization for through-glass vias on thin glass
JP6798730B2 (ja) * 2018-12-13 2020-12-09 ウルトラメモリ株式会社 半導体モジュール及びその製造方法
WO2020171940A1 (en) 2019-02-21 2020-08-27 Corning Incorporated Glass or glass ceramic articles with copper-metallized through holes and processes for making the same
WO2020208698A1 (ja) * 2019-04-09 2020-10-15 日本碍子株式会社 接合基板及び接合基板の製造方法
KR102829971B1 (ko) * 2020-07-02 2025-07-08 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
KR102944499B1 (ko) 2021-06-30 2026-03-25 삼성전자주식회사 집적회로 소자 및 이를 포함하는 전자 시스템

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JP2623812B2 (ja) * 1989-01-25 1997-06-25 日本電気株式会社 半導体装置の製造方法
US5746884A (en) * 1996-08-13 1998-05-05 Advanced Micro Devices, Inc. Fluted via formation for superior metal step coverage
JP3445495B2 (ja) * 1997-07-23 2003-09-08 株式会社東芝 半導体装置
JP3036499B2 (ja) * 1997-11-26 2000-04-24 日本電気株式会社 配線用アルミニウム膜の形成方法及びアルミニウム配線を有する半導体装置
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JP2000332008A (ja) * 1999-05-20 2000-11-30 Fujitsu Ltd 半導体装置及びその製造方法
JP2001244334A (ja) * 2000-03-02 2001-09-07 Toshiba Corp 半導体装置及びその製造方法
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JP2007027291A (ja) * 2005-07-14 2007-02-01 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
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JP4272191B2 (ja) 2005-08-30 2009-06-03 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP4523535B2 (ja) 2005-08-30 2010-08-11 富士通株式会社 半導体装置の製造方法
JP5355892B2 (ja) 2005-09-16 2013-11-27 ルネサスエレクトロニクス株式会社 配線構造並びに半導体装置及びその製造方法
JP2008091835A (ja) 2006-10-05 2008-04-17 Toshiba Corp 半導体装置およびその製造方法
JP5117421B2 (ja) * 2009-02-12 2013-01-16 株式会社東芝 磁気抵抗効果素子及びその製造方法
JP2012129465A (ja) * 2010-12-17 2012-07-05 Elpida Memory Inc 半導体装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11183381B2 (en) 2019-03-15 2021-11-23 Kabushiki Kaisha Toshiba Semiconductor device

Also Published As

Publication number Publication date
US9024443B2 (en) 2015-05-05
JP2014053369A (ja) 2014-03-20
US20140061929A1 (en) 2014-03-06

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