JP5805105B2 - 高アスペクト比ナノ構造におけるパターン崩壊の低減方法 - Google Patents

高アスペクト比ナノ構造におけるパターン崩壊の低減方法 Download PDF

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JP5805105B2
JP5805105B2 JP2012551206A JP2012551206A JP5805105B2 JP 5805105 B2 JP5805105 B2 JP 5805105B2 JP 2012551206 A JP2012551206 A JP 2012551206A JP 2012551206 A JP2012551206 A JP 2012551206A JP 5805105 B2 JP5805105 B2 JP 5805105B2
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wafer
primer
wet
silicon
feature
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JP2013519217A (ja
JP2013519217A5 (https=
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ヤッセリ・アミ−ル・エー．
チュ・ジ
ユイン・ソークミン
ムイ・デビッド・エス．エル．
ミハイリチェンコ・カトリーナ
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Lam Research Corp
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Lam Research Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/18—Cleaning before device manufacture, i.e. Begin-Of-Line process by combined dry cleaning and wet cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/12—Cleaning before device manufacture, i.e. Begin-Of-Line process by dry cleaning only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/15—Cleaning before device manufacture, i.e. Begin-Of-Line process by wet cleaning only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks

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  • Cleaning Or Drying Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
JP2012551206A 2010-02-01 2011-01-21 高アスペクト比ナノ構造におけるパターン崩壊の低減方法 Active JP5805105B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/697,862 US8617993B2 (en) 2010-02-01 2010-02-01 Method of reducing pattern collapse in high aspect ratio nanostructures
US12/697,862 2010-02-01
PCT/US2011/022075 WO2011094132A2 (en) 2010-02-01 2011-01-21 Method of reducing pattern collapse in high aspect ratio nanostructures

Publications (3)

Publication Number Publication Date
JP2013519217A JP2013519217A (ja) 2013-05-23
JP2013519217A5 JP2013519217A5 (https=) 2014-03-06
JP5805105B2 true JP5805105B2 (ja) 2015-11-04

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JP2012551206A Active JP5805105B2 (ja) 2010-02-01 2011-01-21 高アスペクト比ナノ構造におけるパターン崩壊の低減方法

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Country Link
US (1) US8617993B2 (https=)
JP (1) JP5805105B2 (https=)
KR (1) KR101827020B1 (https=)
CN (1) CN102741984B (https=)
SG (1) SG182670A1 (https=)
TW (1) TWI571925B (https=)
WO (1) WO2011094132A2 (https=)

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Also Published As

Publication number Publication date
WO2011094132A2 (en) 2011-08-04
CN102741984A (zh) 2012-10-17
US20110189858A1 (en) 2011-08-04
KR101827020B1 (ko) 2018-03-22
TWI571925B (zh) 2017-02-21
TW201140682A (en) 2011-11-16
US8617993B2 (en) 2013-12-31
JP2013519217A (ja) 2013-05-23
WO2011094132A3 (en) 2011-10-13
SG182670A1 (en) 2012-08-30
KR20120116457A (ko) 2012-10-22
CN102741984B (zh) 2015-05-13

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