TWI571925B - 使高深寬比之奈米結構之圖案崩塌減少發生的方法 - Google Patents

使高深寬比之奈米結構之圖案崩塌減少發生的方法 Download PDF

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Publication number
TWI571925B
TWI571925B TW100103679A TW100103679A TWI571925B TW I571925 B TWI571925 B TW I571925B TW 100103679 A TW100103679 A TW 100103679A TW 100103679 A TW100103679 A TW 100103679A TW I571925 B TWI571925 B TW I571925B
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Taiwan
Prior art keywords
wafer
processing
aspect ratio
sidewalls
semiconductor device
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TW100103679A
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English (en)
Chinese (zh)
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TW201140682A (en
Inventor
阿米爾A 雅薩瑞
朱濟
允錫民
梅世禮
卡翠那 米凱俐茜可
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蘭姆研究公司
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Publication of TW201140682A publication Critical patent/TW201140682A/zh
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Publication of TWI571925B publication Critical patent/TWI571925B/zh

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00Cleaning of wafers, substrates or parts of devices
    • H10P70/10Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/18Cleaning before device manufacture, i.e. Begin-Of-Line process by combined dry cleaning and wet cleaning
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00Cleaning of wafers, substrates or parts of devices
    • H10P70/20Cleaning during device manufacture
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326Deposition processes
    • H10P14/6342Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00Cleaning of wafers, substrates or parts of devices
    • H10P70/10Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/12Cleaning before device manufacture, i.e. Begin-Of-Line process by dry cleaning only
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00Cleaning of wafers, substrates or parts of devices
    • H10P70/10Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/15Cleaning before device manufacture, i.e. Begin-Of-Line process by wet cleaning only
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks

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  • Cleaning Or Drying Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
TW100103679A 2010-02-01 2011-01-31 使高深寬比之奈米結構之圖案崩塌減少發生的方法 TWI571925B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/697,862 US8617993B2 (en) 2010-02-01 2010-02-01 Method of reducing pattern collapse in high aspect ratio nanostructures

Publications (2)

Publication Number Publication Date
TW201140682A TW201140682A (en) 2011-11-16
TWI571925B true TWI571925B (zh) 2017-02-21

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TW100103679A TWI571925B (zh) 2010-02-01 2011-01-31 使高深寬比之奈米結構之圖案崩塌減少發生的方法

Country Status (7)

Country Link
US (1) US8617993B2 (https=)
JP (1) JP5805105B2 (https=)
KR (1) KR101827020B1 (https=)
CN (1) CN102741984B (https=)
SG (1) SG182670A1 (https=)
TW (1) TWI571925B (https=)
WO (1) WO2011094132A2 (https=)

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Also Published As

Publication number Publication date
WO2011094132A2 (en) 2011-08-04
CN102741984A (zh) 2012-10-17
US20110189858A1 (en) 2011-08-04
KR101827020B1 (ko) 2018-03-22
JP5805105B2 (ja) 2015-11-04
TW201140682A (en) 2011-11-16
US8617993B2 (en) 2013-12-31
JP2013519217A (ja) 2013-05-23
WO2011094132A3 (en) 2011-10-13
SG182670A1 (en) 2012-08-30
KR20120116457A (ko) 2012-10-22
CN102741984B (zh) 2015-05-13

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