JP5788151B2 - Dimmにおける相変化メモリ - Google Patents
Dimmにおける相変化メモリ Download PDFInfo
- Publication number
- JP5788151B2 JP5788151B2 JP2010151680A JP2010151680A JP5788151B2 JP 5788151 B2 JP5788151 B2 JP 5788151B2 JP 2010151680 A JP2010151680 A JP 2010151680A JP 2010151680 A JP2010151680 A JP 2010151680A JP 5788151 B2 JP5788151 B2 JP 5788151B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- pcm
- module
- dimm
- dram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40607—Refresh operations in memory devices with an internal cache or data buffer
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/202—Non-volatile memory
- G06F2212/2024—Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/30—Providing cache or TLB in specific location of a processing system
- G06F2212/304—In main memory subsystem
- G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Memory System (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Hardware Redundancy (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/504,029 US8626997B2 (en) | 2009-07-16 | 2009-07-16 | Phase change memory in a dual inline memory module |
| US12/504,029 | 2009-07-16 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015149065A Division JP2016001485A (ja) | 2009-07-16 | 2015-07-29 | 相変化メモリモジュールを備えるシステム、及び相変化メモリモジュールを管理する方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011022998A JP2011022998A (ja) | 2011-02-03 |
| JP2011022998A5 JP2011022998A5 (enExample) | 2013-08-08 |
| JP5788151B2 true JP5788151B2 (ja) | 2015-09-30 |
Family
ID=43448435
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010151680A Active JP5788151B2 (ja) | 2009-07-16 | 2010-07-02 | Dimmにおける相変化メモリ |
| JP2015149065A Pending JP2016001485A (ja) | 2009-07-16 | 2015-07-29 | 相変化メモリモジュールを備えるシステム、及び相変化メモリモジュールを管理する方法 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015149065A Pending JP2016001485A (ja) | 2009-07-16 | 2015-07-29 | 相変化メモリモジュールを備えるシステム、及び相変化メモリモジュールを管理する方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (4) | US8626997B2 (enExample) |
| JP (2) | JP5788151B2 (enExample) |
| KR (1) | KR101504781B1 (enExample) |
| CN (1) | CN101957726B (enExample) |
| DE (1) | DE102010030742B4 (enExample) |
| TW (1) | TWI506626B (enExample) |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9529708B2 (en) | 2011-09-30 | 2016-12-27 | Intel Corporation | Apparatus for configuring partitions within phase change memory of tablet computer with integrated memory controller emulating mass storage to storage driver based on request from software |
| EP2761467B1 (en) | 2011-09-30 | 2019-10-23 | Intel Corporation | Generation of far memory access signals based on usage statistic tracking |
| EP2761464B1 (en) | 2011-09-30 | 2018-10-24 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy having different operating modes |
| EP2761480A4 (en) * | 2011-09-30 | 2015-06-24 | Intel Corp | APPARATUS AND METHOD FOR IMPLEMENTING MULTINIVE MEMORY HIERARCHY ON COMMON MEMORY CHANNELS |
| EP2761466B1 (en) | 2011-09-30 | 2020-08-05 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy |
| EP2761476B1 (en) | 2011-09-30 | 2017-10-25 | Intel Corporation | Apparatus, method and system that stores bios in non-volatile random access memory |
| CN107391397B (zh) | 2011-09-30 | 2021-07-27 | 英特尔公司 | 支持近存储器和远存储器访问的存储器通道 |
| CN102521142B (zh) * | 2011-12-13 | 2015-05-13 | 曙光信息产业(北京)有限公司 | 一种提高大容量、多内存设备访问效率的方法 |
| US9280497B2 (en) * | 2012-12-21 | 2016-03-08 | Dell Products Lp | Systems and methods for support of non-volatile memory on a DDR memory channel |
| CN105808455B (zh) * | 2014-12-31 | 2020-04-28 | 华为技术有限公司 | 访问内存的方法、存储级内存及计算机系统 |
| KR102408613B1 (ko) * | 2015-08-27 | 2022-06-15 | 삼성전자주식회사 | 메모리 모듈의 동작 방법, 및 메모리 모듈을 제어하는 프로세서의 동작 방법, 및 사용자 시스템 |
| US10095618B2 (en) | 2015-11-25 | 2018-10-09 | Intel Corporation | Memory card with volatile and non volatile memory space having multiple usage model configurations |
| US9747041B2 (en) | 2015-12-23 | 2017-08-29 | Intel Corporation | Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device |
| US10007606B2 (en) | 2016-03-30 | 2018-06-26 | Intel Corporation | Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory |
| US10185619B2 (en) | 2016-03-31 | 2019-01-22 | Intel Corporation | Handling of error prone cache line slots of memory side cache of multi-level system memory |
| US10120806B2 (en) | 2016-06-27 | 2018-11-06 | Intel Corporation | Multi-level system memory with near memory scrubbing based on predicted far memory idle time |
| US10193248B2 (en) | 2016-08-31 | 2019-01-29 | Crystal Group, Inc. | System and method for retaining memory modules |
| CN106328183B (zh) * | 2016-09-23 | 2018-08-31 | 山东师范大学 | 一种改进的存储器系统及方法 |
| US10915453B2 (en) | 2016-12-29 | 2021-02-09 | Intel Corporation | Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structures |
| US10445261B2 (en) | 2016-12-30 | 2019-10-15 | Intel Corporation | System memory having point-to-point link that transports compressed traffic |
| KR20180127707A (ko) * | 2017-05-22 | 2018-11-30 | 에스케이하이닉스 주식회사 | 메모리 모듈 및 이의 동작 방법 |
| US10304814B2 (en) | 2017-06-30 | 2019-05-28 | Intel Corporation | I/O layout footprint for multiple 1LM/2LM configurations |
| US11188467B2 (en) | 2017-09-28 | 2021-11-30 | Intel Corporation | Multi-level system memory with near memory capable of storing compressed cache lines |
| US10860244B2 (en) | 2017-12-26 | 2020-12-08 | Intel Corporation | Method and apparatus for multi-level memory early page demotion |
| US10990463B2 (en) | 2018-03-27 | 2021-04-27 | Samsung Electronics Co., Ltd. | Semiconductor memory module and memory system including the same |
| KR102505913B1 (ko) | 2018-04-04 | 2023-03-07 | 삼성전자주식회사 | 메모리 모듈 및 메모리 모듈을 포함하는 메모리 시스템 |
| US10734756B2 (en) | 2018-08-10 | 2020-08-04 | Crystal Group Inc. | DIMM/expansion card retention method for highly kinematic environments |
| US11307977B2 (en) * | 2018-09-27 | 2022-04-19 | Intel Corporation | Technologies for direct matrix read and write operations |
| US11055228B2 (en) | 2019-01-31 | 2021-07-06 | Intel Corporation | Caching bypass mechanism for a multi-level memory |
| US11093323B2 (en) * | 2019-04-15 | 2021-08-17 | Nvidia Corporation | Performant inline ECC architecture for DRAM controller |
| US11823767B2 (en) * | 2021-04-01 | 2023-11-21 | Micron Technology, Inc. | Dynamic random access memory speed bin compatibility |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06215589A (ja) | 1993-01-18 | 1994-08-05 | Hitachi Ltd | 半導体メモリ |
| IN188196B (enExample) * | 1995-05-15 | 2002-08-31 | Silicon Graphics Inc | |
| US5758056A (en) * | 1996-02-08 | 1998-05-26 | Barr; Robert C. | Memory system having defective address identification and replacement |
| US6000006A (en) | 1997-08-25 | 1999-12-07 | Bit Microsystems, Inc. | Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage |
| US6603757B1 (en) * | 1999-04-14 | 2003-08-05 | Excel Switching Corporation | Voice-data access concentrator for node in an expandable telecommunications system |
| US6765812B2 (en) | 2001-01-17 | 2004-07-20 | Honeywell International Inc. | Enhanced memory module architecture |
| JP4143287B2 (ja) * | 2001-11-08 | 2008-09-03 | エルピーダメモリ株式会社 | 半導体記憶装置とそのデータ読み出し制御方法 |
| US6909656B2 (en) * | 2002-01-04 | 2005-06-21 | Micron Technology, Inc. | PCRAM rewrite prevention |
| US7336098B2 (en) * | 2004-06-30 | 2008-02-26 | Intel Corporation | High speed memory modules utilizing on-pin capacitors |
| US7224595B2 (en) * | 2004-07-30 | 2007-05-29 | International Business Machines Corporation | 276-Pin buffered memory module with enhanced fault tolerance |
| TWI273435B (en) * | 2004-12-28 | 2007-02-11 | Inventec Corp | Access control method for dynamic random access memory module |
| CN100437532C (zh) * | 2004-12-30 | 2008-11-26 | 英业达股份有限公司 | 动态随机存取存储器的存取控制方法 |
| JP4428284B2 (ja) * | 2005-04-25 | 2010-03-10 | エルピーダメモリ株式会社 | 半導体記憶装置およびその書込み方法 |
| US8244971B2 (en) * | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
| WO2007002324A2 (en) * | 2005-06-24 | 2007-01-04 | Metaram, Inc. | An integrated memory core and memory interface circuit |
| KR100671747B1 (ko) | 2006-01-04 | 2007-01-19 | 삼성전자주식회사 | 개선된 애디티브 레이턴시를 가진 메모리 시스템 및제어방법 |
| WO2008051940A2 (en) | 2006-10-23 | 2008-05-02 | Virident Systems, Inc. | Methods and apparatus of dual inline memory modules for flash memory |
| JP5669338B2 (ja) * | 2007-04-26 | 2015-02-12 | 株式会社日立製作所 | 半導体装置 |
| US8209479B2 (en) * | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
| JP5049733B2 (ja) * | 2007-10-17 | 2012-10-17 | 株式会社東芝 | 情報処理システム |
| JP4234766B1 (ja) | 2007-10-31 | 2009-03-04 | 株式会社東芝 | 電子機器およびその制御方法 |
| CN102177551B (zh) * | 2008-08-08 | 2015-05-20 | 惠普开发有限公司 | 与标准存储器模块管脚兼容的存储器模块中的独立可控制和可重新配置的虚拟存储器设备 |
| US8225031B2 (en) * | 2008-10-30 | 2012-07-17 | Hewlett-Packard Development Company, L.P. | Memory module including environmental optimization |
| US8694737B2 (en) * | 2010-06-09 | 2014-04-08 | Micron Technology, Inc. | Persistent memory for processor main memory |
| US8688899B2 (en) * | 2010-09-28 | 2014-04-01 | Fusion-Io, Inc. | Apparatus, system, and method for an interface between a memory controller and a non-volatile memory controller using a command protocol |
-
2009
- 2009-07-16 US US12/504,029 patent/US8626997B2/en active Active
-
2010
- 2010-06-01 KR KR1020100051646A patent/KR101504781B1/ko active Active
- 2010-06-30 DE DE102010030742.4A patent/DE102010030742B4/de active Active
- 2010-06-30 TW TW099121412A patent/TWI506626B/zh active
- 2010-07-02 JP JP2010151680A patent/JP5788151B2/ja active Active
- 2010-07-05 CN CN201010222395.1A patent/CN101957726B/zh active Active
-
2013
- 2013-12-04 US US14/097,125 patent/US9576662B2/en active Active
-
2015
- 2015-07-29 JP JP2015149065A patent/JP2016001485A/ja active Pending
-
2016
- 2016-12-28 US US15/392,697 patent/US10437722B2/en active Active
-
2019
- 2019-07-22 US US16/518,869 patent/US11494302B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US10437722B2 (en) | 2019-10-08 |
| US11494302B2 (en) | 2022-11-08 |
| JP2016001485A (ja) | 2016-01-07 |
| KR101504781B1 (ko) | 2015-03-20 |
| US20140095781A1 (en) | 2014-04-03 |
| TWI506626B (zh) | 2015-11-01 |
| CN101957726B (zh) | 2015-09-02 |
| US20200019501A1 (en) | 2020-01-16 |
| DE102010030742B4 (de) | 2018-04-05 |
| US20110016268A1 (en) | 2011-01-20 |
| US9576662B2 (en) | 2017-02-21 |
| JP2011022998A (ja) | 2011-02-03 |
| KR20110007571A (ko) | 2011-01-24 |
| US8626997B2 (en) | 2014-01-07 |
| CN101957726A (zh) | 2011-01-26 |
| TW201115577A (en) | 2011-05-01 |
| US20170177478A1 (en) | 2017-06-22 |
| DE102010030742A1 (de) | 2011-02-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5788151B2 (ja) | Dimmにおける相変化メモリ | |
| US11768603B2 (en) | Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory | |
| US9772803B2 (en) | Semiconductor memory device and memory system | |
| US11061763B2 (en) | Memory controller, memory system and application processor comprising the memory controller | |
| US8645637B2 (en) | Interruption of write memory operations to provide faster read access in a serial interface memory | |
| US11275678B2 (en) | Data storage device with spare blocks for replacing bad block in super block and operating method thereof | |
| US9064603B1 (en) | Semiconductor memory device and memory system including the same | |
| US10545689B2 (en) | Data storage device and operating method thereof | |
| US8085584B1 (en) | Memory to store user-configurable data polarity | |
| KR20160144560A (ko) | 호스트에 의해 접근되는 오류 정보를 생성하는 불휘발성 메모리 모듈, 스토리지 장치, 및 전자 장치 | |
| US11640253B2 (en) | Method to use flat relink table in HMB | |
| JP5464527B2 (ja) | 不揮発性メモリの読み出し動作変更 | |
| KR102303653B1 (ko) | 메모리 장치 및 이를 포함하는 메모리 시스템 | |
| KR20160144557A (ko) | 읽기 데이터를 전송 단위로 전송하는 불휘발성 메모리 모듈, 스토리지 장치, 및 전자 장치 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20111215 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120119 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130625 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130625 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140325 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140416 |
|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20140416 |
|
| RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20140421 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140625 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20140625 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20140701 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140725 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150106 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150318 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150630 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150729 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5788151 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |