JP5785496B2 - ファセットされたシリサイドコンタクトを有する半導体デバイス及び関連する製造方法 - Google Patents

ファセットされたシリサイドコンタクトを有する半導体デバイス及び関連する製造方法 Download PDF

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JP5785496B2
JP5785496B2 JP2011531097A JP2011531097A JP5785496B2 JP 5785496 B2 JP5785496 B2 JP 5785496B2 JP 2011531097 A JP2011531097 A JP 2011531097A JP 2011531097 A JP2011531097 A JP 2011531097A JP 5785496 B2 JP5785496 B2 JP 5785496B2
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semiconductor material
recess
semiconductor
layer
region
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JP2012505547A (ja
JP2012505547A5 (https=
Inventor
ビン ヤン フランク
ビン ヤン フランク
パル ロヒト
パル ロヒト
ハーグローブ マイケル
ハーグローブ マイケル
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2926—Crystal orientations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3466—Crystal orientation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3408—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
JP2011531097A 2008-10-10 2009-10-05 ファセットされたシリサイドコンタクトを有する半導体デバイス及び関連する製造方法 Expired - Fee Related JP5785496B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/249,570 US7994014B2 (en) 2008-10-10 2008-10-10 Semiconductor devices having faceted silicide contacts, and related fabrication methods
US12/249,570 2008-10-10
PCT/US2009/059560 WO2010051133A2 (en) 2008-10-10 2009-10-05 Semiconductor devices having faceted silicide contacts, and related fabrication methods

Publications (3)

Publication Number Publication Date
JP2012505547A JP2012505547A (ja) 2012-03-01
JP2012505547A5 JP2012505547A5 (https=) 2012-11-22
JP5785496B2 true JP5785496B2 (ja) 2015-09-30

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JP2011531097A Expired - Fee Related JP5785496B2 (ja) 2008-10-10 2009-10-05 ファセットされたシリサイドコンタクトを有する半導体デバイス及び関連する製造方法

Country Status (6)

Country Link
US (1) US7994014B2 (https=)
EP (1) EP2345065A2 (https=)
JP (1) JP5785496B2 (https=)
KR (1) KR101639771B1 (https=)
CN (1) CN102177573B (https=)
WO (1) WO2010051133A2 (https=)

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US7445978B2 (en) * 2005-05-04 2008-11-04 Chartered Semiconductor Manufacturing, Ltd Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS
DE102009031114B4 (de) * 2009-06-30 2011-07-07 Globalfoundries Dresden Module One LLC & CO. KG, 01109 Halbleiterelement, das in einem kristallinen Substratmaterial hergestellt ist und ein eingebettetes in-situ n-dotiertes Halbleitermaterial aufweist, und Verfahren zur Herstellung desselben
US8361867B2 (en) * 2010-03-19 2013-01-29 Acorn Technologies, Inc. Biaxial strained field effect transistor devices
US8492234B2 (en) * 2010-06-29 2013-07-23 International Business Machines Corporation Field effect transistor device
DE102010030768B4 (de) 2010-06-30 2012-05-31 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Herstellverfahren für ein Halbleiterbauelement als Transistor mit eingebettetem Si/Ge-Material mit geringerem Abstand und besserer Gleichmäßigkeit und Transistor
DE102011076695B4 (de) * 2011-05-30 2013-05-08 Globalfoundries Inc. Transistoren mit eingebettetem verformungsinduzierenden Material, das in durch einen Oxidationsätzprozess erzeugten Aussparungen ausgebildet ist
US9190471B2 (en) * 2012-04-13 2015-11-17 Globalfoundries U.S.2 Llc Semiconductor structure having a source and a drain with reverse facets
US9012999B2 (en) * 2012-08-21 2015-04-21 Stmicroelectronics, Inc. Semiconductor device with an inclined source/drain and associated methods
US20140057399A1 (en) * 2012-08-24 2014-02-27 International Business Machines Corporation Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer
US20140170826A1 (en) * 2012-12-19 2014-06-19 Acorn Technologies, Inc. Biaxial strained field effect transistor devices
US9627480B2 (en) * 2014-06-26 2017-04-18 Globalfoundries Inc. Junction butting structure using nonuniform trench shape
US9647073B2 (en) 2014-10-29 2017-05-09 Globalfoundries Inc. Transistor structures and fabrication methods thereof
CN105762106B (zh) * 2014-12-18 2021-02-19 联华电子股份有限公司 半导体装置及其制作工艺
CN107636804B (zh) * 2015-06-27 2022-06-07 英特尔公司 用以使用量化金属形成与半导体的欧姆接触的方法
CN107275210B (zh) * 2016-04-06 2023-05-02 联华电子股份有限公司 半导体元件及其制作方法
US10643893B2 (en) 2016-06-29 2020-05-05 International Business Machines Corporation Surface area and Schottky barrier height engineering for contact trench epitaxy
US10396208B2 (en) 2017-01-13 2019-08-27 International Business Machines Corporation Vertical transistors with improved top source/drain junctions
KR102257419B1 (ko) 2017-06-07 2021-05-31 삼성전자주식회사 반도체 장치 및 그 제조 방법
US10217660B2 (en) * 2017-07-18 2019-02-26 Globalfoundries Inc. Technique for patterning active regions of transistor elements in a late manufacturing stage
US10580977B2 (en) 2018-07-24 2020-03-03 International Business Machines Corporation Tightly integrated 1T1R ReRAM for planar technology
US10777642B2 (en) * 2019-01-30 2020-09-15 Globalfoundries Inc. Formation of enhanced faceted raised source/drain epi material for transistor devices
US10825897B2 (en) 2019-01-30 2020-11-03 Globalfoundries Inc. Formation of enhanced faceted raised source/drain EPI material for transistor devices

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US5323053A (en) * 1992-05-28 1994-06-21 At&T Bell Laboratories Semiconductor devices using epitaxial silicides on (111) surfaces etched in (100) silicon substrates
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Also Published As

Publication number Publication date
EP2345065A2 (en) 2011-07-20
US7994014B2 (en) 2011-08-09
US20100090289A1 (en) 2010-04-15
CN102177573B (zh) 2014-01-22
WO2010051133A3 (en) 2010-10-07
KR20110091667A (ko) 2011-08-12
KR101639771B1 (ko) 2016-07-14
JP2012505547A (ja) 2012-03-01
CN102177573A (zh) 2011-09-07
WO2010051133A2 (en) 2010-05-06

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