JP5784998B2 - 素子実装用基板 - Google Patents
素子実装用基板 Download PDFInfo
- Publication number
- JP5784998B2 JP5784998B2 JP2011134692A JP2011134692A JP5784998B2 JP 5784998 B2 JP5784998 B2 JP 5784998B2 JP 2011134692 A JP2011134692 A JP 2011134692A JP 2011134692 A JP2011134692 A JP 2011134692A JP 5784998 B2 JP5784998 B2 JP 5784998B2
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- substrate
- mounting
- wiring pattern
- base metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
2 銅メッキ層
3 ニッケルメッキ層
4 金メッキ層
5 チップ部品
6 レジスト膜
10,20 素子実装用基板
11a 素子実装面
12 配線パターン
13 下地金属層
14 硬質金属層
15 表面金属層
16,26 素子
17 バンプ
27 ワイヤー
P 実装ポイント
Claims (2)
- 基板と、
該基板の素子実装面上に形成された配線パターンとを有し、
前記配線パターンが、前記基板の素子実装面上に形成された高い熱伝導率を有する銅からなる下地金属層と、前記配線パターンにおける素子に接続するワイヤーの実装ポイントにのみ配置され、前記下地金属層の上に形成された硬度が高く熱伝導率が低いニッケルからなる硬質金属層と、前記下地金属層に沿って前記下地金属層及び前記硬質金属層を覆うように形成された高い熱伝導率を有する金又は銀からなる表面金属層と、から構成され、
前記配線パターンにおける前記素子をダイボンディングする部分が前記下地金属層と前記表面金属層だけの積層構造となることを特徴とする素子実装用基板。 - 前記基板上に実装される素子がLEDである請求項1に記載の素子実装用基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011134692A JP5784998B2 (ja) | 2011-06-17 | 2011-06-17 | 素子実装用基板 |
Applications Claiming Priority (1)
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---|---|---|---|
JP2011134692A JP5784998B2 (ja) | 2011-06-17 | 2011-06-17 | 素子実装用基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013004756A JP2013004756A (ja) | 2013-01-07 |
JP5784998B2 true JP5784998B2 (ja) | 2015-09-24 |
Family
ID=47672997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011134692A Active JP5784998B2 (ja) | 2011-06-17 | 2011-06-17 | 素子実装用基板 |
Country Status (1)
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JP (1) | JP5784998B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8837261B1 (en) * | 2013-08-27 | 2014-09-16 | HGST Netherlands B.V. | Electrical contact for an energy-assisted magnetic recording laser sub-mount |
JP6565735B2 (ja) * | 2016-02-24 | 2019-08-28 | 三菱マテリアル株式会社 | パワーモジュール用基板及びパワーモジュール並びにパワーモジュール用基板の製造方法 |
JP6969471B2 (ja) * | 2018-03-23 | 2021-11-24 | 三菱マテリアル株式会社 | 絶縁回路基板 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09213730A (ja) * | 1996-02-01 | 1997-08-15 | Matsushita Electron Corp | 高周波用モジュール基板およびそれを用いた高周波電力増幅モジュール |
JPH10335522A (ja) * | 1997-05-29 | 1998-12-18 | Matsushita Electric Ind Co Ltd | Ic実装用基板 |
JP3878436B2 (ja) * | 2001-06-05 | 2007-02-07 | 日立電線株式会社 | 配線基板および半導体装置 |
JP3692978B2 (ja) * | 2001-07-24 | 2005-09-07 | 日立電線株式会社 | 配線基板の製造方法 |
US8592691B2 (en) * | 2009-02-27 | 2013-11-26 | Ibiden Co., Ltd. | Printed wiring board |
JP2011091091A (ja) * | 2009-10-20 | 2011-05-06 | Japan Radio Co Ltd | 電子部品の実装構造及び実装方法 |
-
2011
- 2011-06-17 JP JP2011134692A patent/JP5784998B2/ja active Active
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JP2013004756A (ja) | 2013-01-07 |
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