JP5773306B2 - 半導体素子構造を形成する方法および装置 - Google Patents

半導体素子構造を形成する方法および装置 Download PDF

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JP5773306B2
JP5773306B2 JP2011004797A JP2011004797A JP5773306B2 JP 5773306 B2 JP5773306 B2 JP 5773306B2 JP 2011004797 A JP2011004797 A JP 2011004797A JP 2011004797 A JP2011004797 A JP 2011004797A JP 5773306 B2 JP5773306 B2 JP 5773306B2
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layer
dielectric
copper
substrate
metal
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JP2011004797A
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Japanese (ja)
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JP2011146711A (ja
JP2011146711A5 (https=
Inventor
バナージ、アナンダ
アンドリュー アントネリ、ジョージ
アンドリュー アントネリ、ジョージ
ローリン、ジェニファー オ
ローリン、ジェニファー オ
スリラム、マンディヤム
シュラヴェンディジク、バート ヴァン
シュラヴェンディジク、バート ヴァン
ヴァラダラジャン、セシャサイー
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Novellus Systems Inc
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Novellus Systems Inc
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Priority claimed from US12/688,154 external-priority patent/US8268722B2/en
Priority claimed from US12/689,803 external-priority patent/US7858510B1/en
Application filed by Novellus Systems Inc filed Critical Novellus Systems Inc
Publication of JP2011146711A publication Critical patent/JP2011146711A/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01354—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6316—Formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6512—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a gas or vapour
    • H10P14/6514—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a gas or vapour by exposure to a plasma
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/12—Cleaning before device manufacture, i.e. Begin-Of-Line process by dry cleaning only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2011004797A 2010-01-15 2011-01-13 半導体素子構造を形成する方法および装置 Expired - Fee Related JP5773306B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/688,154 2010-01-15
US12/688,154 US8268722B2 (en) 2009-06-03 2010-01-15 Interfacial capping layers for interconnects
US12/689,803 US7858510B1 (en) 2008-02-28 2010-01-19 Interfacial layers for electromigration resistance improvement in damascene interconnects
US12/689,803 2010-01-19

Publications (3)

Publication Number Publication Date
JP2011146711A JP2011146711A (ja) 2011-07-28
JP2011146711A5 JP2011146711A5 (https=) 2014-02-27
JP5773306B2 true JP5773306B2 (ja) 2015-09-02

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JP2011004797A Expired - Fee Related JP5773306B2 (ja) 2010-01-15 2011-01-13 半導体素子構造を形成する方法および装置

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Country Link
JP (1) JP5773306B2 (https=)
KR (1) KR101742825B1 (https=)
CN (1) CN102130046B (https=)
TW (2) TW201709418A (https=)

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US7727881B1 (en) 2004-11-03 2010-06-01 Novellus Systems, Inc. Protective self-aligned buffer layers for damascene interconnects
US7727880B1 (en) 2004-11-03 2010-06-01 Novellus Systems, Inc. Protective self-aligned buffer layers for damascene interconnects
WO2012167141A2 (en) 2011-06-03 2012-12-06 Novellus Systems, Inc. Metal and silicon containing capping layers for interconnects
CN104008995B (zh) * 2013-02-22 2017-09-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
JP2016514352A (ja) * 2013-03-05 2016-05-19 インテグリス・インコーポレーテッド イオン注入のための組成物、システムおよび方法
CN105378907A (zh) * 2013-07-24 2016-03-02 应用材料公司 钴基板处理系统、设备及方法
CN104576514B (zh) * 2013-10-29 2017-11-24 中芯国际集成电路制造(上海)有限公司 半导体器件的制备方法
CN104637864B (zh) * 2013-11-14 2017-11-24 中芯国际集成电路制造(上海)有限公司 提高数据保持能力的方法
US9368448B2 (en) * 2013-12-20 2016-06-14 Applied Materials, Inc. Metal-containing films as dielectric capping barrier for advanced interconnects
US9465071B2 (en) * 2014-03-04 2016-10-11 Mediatek Inc. Method and apparatus for generating featured scan pattern
US10319908B2 (en) * 2014-05-01 2019-06-11 Crossbar, Inc. Integrative resistive memory in backend metal layers
US9633896B1 (en) 2015-10-09 2017-04-25 Lam Research Corporation Methods for formation of low-k aluminum-containing etch stop films
WO2018063815A1 (en) * 2016-10-02 2018-04-05 Applied Materials, Inc. Doped selective metal caps to improve copper electromigration with ruthenium liner
US9859153B1 (en) * 2016-11-14 2018-01-02 Lam Research Corporation Deposition of aluminum oxide etch stop layers
CN107256845A (zh) * 2017-05-25 2017-10-17 上海集成电路研发中心有限公司 一种铜互连结构及其制造方法
US20190127212A1 (en) * 2017-10-31 2019-05-02 Texas Instruments Incorporated Forming a passivation coating for mems devices
US10741440B2 (en) * 2018-06-05 2020-08-11 Lam Research Corporation Metal liner passivation and adhesion enhancement by zinc doping
US10707119B1 (en) * 2019-01-14 2020-07-07 Globalfoundries Inc. Interconnect structures with airgaps and dielectric-capped interconnects
CN111769074B (zh) * 2019-04-02 2024-09-27 长鑫存储技术有限公司 半导体互连结构及其制作方法
KR102812547B1 (ko) * 2020-04-21 2025-05-27 프랙스에어 테크놀로지, 인코포레이티드 실리콘-게르마늄 층의 기상 선택적 식각을 위한 신규한 방법
CN114429990B (zh) * 2020-10-29 2026-01-23 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11581258B2 (en) * 2021-01-13 2023-02-14 Nanya Technology Corporation Semiconductor device structure with manganese-containing interconnect structure and method for forming the same
US11961735B2 (en) * 2021-06-04 2024-04-16 Tokyo Electron Limited Cyclic plasma processing

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JPH0765179B2 (ja) * 1987-05-15 1995-07-12 日本電信電話株式会社 化学的気相成長方法
US6605531B1 (en) * 1997-11-26 2003-08-12 Applied Materials, Inc. Hole-filling technique using CVD aluminum and PVD aluminum integration
US20020048926A1 (en) * 2000-09-14 2002-04-25 Konecni Anthony J. Method for forming a self-aligned copper capping diffusion barrier
US6664182B2 (en) * 2001-04-25 2003-12-16 Macronix International Co. Ltd. Method of improving the interlayer adhesion property of low-k layers in a dual damascene process
US6518167B1 (en) * 2002-04-16 2003-02-11 Advanced Micro Devices, Inc. Method of forming a metal or metal nitride interface layer between silicon nitride and copper
JP2006505127A (ja) * 2002-10-29 2006-02-09 エーエスエム　インターナショナル　エヌ．ヴェー． 酸素架橋構造及び方法
KR100564801B1 (ko) * 2003-12-30 2006-03-28 동부아남반도체 주식회사 반도체 제조 방법
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Also Published As

Publication number Publication date
CN102130046A (zh) 2011-07-20
TW201709418A (zh) 2017-03-01
KR20110084130A (ko) 2011-07-21
JP2011146711A (ja) 2011-07-28
TWI612618B (zh) 2018-01-21
TW201138024A (en) 2011-11-01
KR101742825B1 (ko) 2017-06-01
CN102130046B (zh) 2015-01-14

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