JP5759581B2 - サンプリング回路のタイミング不整合を減少させるための装置および方法 - Google Patents
サンプリング回路のタイミング不整合を減少させるための装置および方法 Download PDFInfo
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- JP5759581B2 JP5759581B2 JP2014045581A JP2014045581A JP5759581B2 JP 5759581 B2 JP5759581 B2 JP 5759581B2 JP 2014045581 A JP2014045581 A JP 2014045581A JP 2014045581 A JP2014045581 A JP 2014045581A JP 5759581 B2 JP5759581 B2 JP 5759581B2
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- 238000005070 sampling Methods 0.000 title claims description 235
- 238000000034 method Methods 0.000 title claims description 21
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- 101100191136 Arabidopsis thaliana PCMP-A2 gene Proteins 0.000 description 21
- 101100048260 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UBX2 gene Proteins 0.000 description 21
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- 230000000630 rising effect Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 101100422768 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SUL2 gene Proteins 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0836—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of phase error, e.g. jitter
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
- H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Electronic Switches (AREA)
- Amplifiers (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361774432P | 2013-03-07 | 2013-03-07 | |
US61/774,432 | 2013-03-07 | ||
US13/975,291 US8866652B2 (en) | 2013-03-07 | 2013-08-24 | Apparatus and method for reducing sampling circuit timing mismatch |
US13/975,291 | 2013-08-24 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2014176096A JP2014176096A (ja) | 2014-09-22 |
JP2014176096A5 JP2014176096A5 (zh) | 2014-12-11 |
JP5759581B2 true JP5759581B2 (ja) | 2015-08-05 |
Family
ID=50472978
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014045581A Active JP5759581B2 (ja) | 2013-03-07 | 2014-03-07 | サンプリング回路のタイミング不整合を減少させるための装置および方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8866652B2 (zh) |
EP (1) | EP2775481B1 (zh) |
JP (1) | JP5759581B2 (zh) |
CN (1) | CN104038219B (zh) |
Families Citing this family (7)
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US9325313B2 (en) * | 2014-01-28 | 2016-04-26 | Broadcom Corporation | Low-power level-shift circuit for data-dependent signals |
US9734783B2 (en) * | 2015-03-19 | 2017-08-15 | Apple Inc. | Displays with high impedance gate driver circuitry |
US10073167B2 (en) * | 2015-05-22 | 2018-09-11 | Texas Instruments Incorporated | High speed illumination driver for TOF applications |
US10547308B2 (en) * | 2017-11-22 | 2020-01-28 | Analog Devices, Inc. | Reconfigurable low power and low area gate bootsrapping circuit |
US10084466B1 (en) * | 2017-12-28 | 2018-09-25 | Texas Instruments Incorporated | Top plate sampling circuit including input-dependent dual clock boost circuits |
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-
2013
- 2013-08-24 US US13/975,291 patent/US8866652B2/en active Active
-
2014
- 2014-02-25 EP EP14156535.8A patent/EP2775481B1/en active Active
- 2014-03-07 JP JP2014045581A patent/JP5759581B2/ja active Active
- 2014-03-07 CN CN201410081559.1A patent/CN104038219B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
EP2775481B1 (en) | 2016-05-04 |
CN104038219A (zh) | 2014-09-10 |
CN104038219B (zh) | 2017-10-27 |
US8866652B2 (en) | 2014-10-21 |
EP2775481A3 (en) | 2015-03-18 |
US20140253353A1 (en) | 2014-09-11 |
EP2775481A2 (en) | 2014-09-10 |
JP2014176096A (ja) | 2014-09-22 |
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