JP5736112B2 - 組み込まれたpn接合を有するショットキダイオード - Google Patents
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- 239000002019 doping agent Substances 0.000 claims description 6
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Description
図1は、第1導電型、ここではn型にドープされたドリフト層3’により分離されたソースコンタクト1’とドレインコンタクト2’とを有する公知の半導体デバイスを示す。ドリフト層は、ここでは1つの副層であり、即ち、高ドープの副層5’である。デバイスは、更に、ドリフト層の上に、ソースコンタクトに属し、ドリフト層に対してショットキコンタクトを形成し、ドリフト層の上で、ここではpである第2導電型のドーパントでドープされた半導体材料の追加の層の形態の領域7’により横方向に分離される複数の金属層を含む。追加の層7’は、好適には高ドープである。
本発明は、この問題を解決するものであり、本発明の第1の具体例にかかるデバイスは、図3に模式的に示される。図1、2の従来技術のデバイスに対応するこのデバイスの部分は、同じ参照符号により示されている。このデバイスの半導体材料はSiCである。このデバイスは、公知のデバイスと、ドリフト層3が2つの副層を有する点、即ち、ソースコンタクトに近い第1の低ドープの副層4と、ドレインコンタクトに近いより高ドープの第2の副層5を有し、少なくとも1つの追加の層7”は実質的により大きな横方向の長さを有し、これによりドリフト層との界面の面積が、隣接する追加の層7よりも大きくなる。
Claims (19)
- nまたはpの第1導電型のドーパントによりドープされたドリフト層(3)により相互接続されたソースコンタクト(1)とドレインコンタクト(2)を有し、デバイスの順バイアス状態で、該ソースコンタクトと該ドレインコンタクトとの間の導電経路を多数電荷キャリアが移動する半導体デバイスであって、
該デバイスは、該ソースコンタクトに接続した複数の金属層領域を該ドリフト層の上に含み、
該複数の金属層領域は、該ドリフト層に対してショットキコンタクト領域(6)を形成し、該ドリフト層の上にある該第1導電型と反対の第2導電型のドーパントでドープされた半導体材料の追加の層(7、7”)により横方向に分離され、該追加の層は該ドリフト層との界面でpn接合を形成し、該デバイスが逆バイアス状態で連続したブロッキングpn接合を形成して該ショットキコンタクト領域(6)を保護し、
該ソースコンタクトは該追加の層の上にも適用された該デバイスにおいて、
該追加の層の少なくとも1つ(7”)は、隣接する該追加の層(7)に比較して、より大きな横方向の長さと、より大きな該ドリフト層との界面の面積を有して、該追加の層の少なくとも1つと該ドリフト層との間で十分な電圧の上昇を容易にして、該デバイスの順方向導電状態のサージ時に、該追加の層の少なくとも1つから該ドリフト層(3)に少数電荷キャリアを注入し、該ドリフト層の抵抗を低減し、これによりサージ時の温度を低減し、該金属層領域は、該追加の層の、ドリフト層の上の面を除く全ての面と、完全に隣り合うことを特徴とする半導体デバイス。 - それぞれの上記追加の層(7、7”)は、上記ドリフト層(3)の上に配置されるとともに、上記ショットキコンタクト領域(6)により横方向に限定された該ドリフト層との界面を形成することを特徴とする請求項1に記載のデバイス。
- 上記ショットキコンタクト領域(6)は、上記ドリフト層(3)中のリセス(11)の底部に配置され、それぞれの該ショットキコンタクト領域(6)は、隣接する上記追加の層(7、7”)を分離し、該追加の層(7、7”)と該ドリフト層(3)との間の界面の下方に配置されることを特徴とする請求項2に記載のデバイス。
- 上記ドリフト層(3)は2つの副層であって、上記ソースコンタクトに近い第1の低ドープ副層(4)と、上記ドレインコンタクトに近い高ドープの第2副層(5)とを有する請求項1〜3のいずれかに記載のデバイス。
- 上記ドリフト層(3)と上記追加の層(7、7”)はSiCから形成され、第1導電型はnであり、第2導電型はpであり、サージ保護のために該ドリフト層に正孔が注入される請求項1〜4のいずれかに記載のデバイス。
- 上記第1の副層(4)は1015cm−3より低いドーピング濃度を有し、上記第2の副層(5)は1016cm−3より高いドーピング濃度を有する請求項4に記載のデバイス。
- 上記ドリフト層(3)の上面に沿った横方向に、少なくとも7つ毎に配置された上記追加の層(7、7”)の1つが、隣接するそれぞれの追加の層のより大きな横方向の長さを有することを特徴とする請求項1〜6のいずれかに記載のデバイス。
- 上記少なくとも1つの追加の層(7”)は、隣接する上記追加の層(7)の横方向の長さの、少なくとも1.5倍の横方向の長さを有することを特徴とする請求項1〜7のいずれかに記載のデバイス。
- 上記少なくとも1つの追加の層(7”)の横方向の長さは、5μmから15μmであり、隣接する上記追加の層(7)の横方向の長さは、2μmから4μmであることを特徴とする請求項1〜8のいずれかに記載のデバイス。
- 隣接する上記追加の層(7、7”)の間の横方向の距離は、上記ドリフト層(3)の上面に沿って一定である請求項1〜9のいずれかに記載のデバイス。
- 上記ショットキコンタクト領域(6)と上記追加の層(7、7”)は、上記ドリフト層(3)の上に同心のリング形状で配置され、それぞれのリングは一定の幅を有し、横方向の距離はそれらのリングの半径方向を意味することを特徴とする請求項1〜10のいずれかに記載のデバイス。
- 隣接する上記追加の層(7、7”)の間の距離は、上記ドリフト層(3)の厚みと同じかまたはより小さいことを特徴とする請求項10に記載のデバイス。
- 上記ドリフト層(3)は、上記ショットキコンタクト領域(6)および上記追加の層(7、7”)と隣り合う薄い低ドープの第1副層(4)と、その下にあり、上記ドレインコンタクト(2)と隣り合う高ドープの第2副層(5)とを有する請求項1〜12のいずれかに記載のデバイス。
- 上記ドリフト層(3)と上記追加の層(7、7”)は、ダイアモンドから形成され、第1導電型はpであり、第2導電型はnであり、サージ保護のために上記ドリフト層に電子が注入される請求項1〜4および7〜13のいずれかに記載のデバイス。
- 上記ドリフト層(3)の上面に沿った横方向に、少なくとも6つ毎に配置された上記追加の層(7、7”)が、隣接するそれぞれの追加の層より大きな横方向の長さを有する請求項1〜6のいずれかに記載のデバイス。
- 上記ドリフト層(3)の上面に沿った横方向に、少なくとも5つ毎に配置された上記追加の層(7、7”)が、隣接するそれぞれの追加の層より大きな横方向の長さを有する請求項1〜6のいずれかに記載のデバイス。
- 上記ドリフト層(3)の上面に沿った横方向に、少なくとも4つ毎に配置された上記追加の層(7、7”)が、隣接するそれぞれの追加の層より大きな横方向の長さを有する請求項1〜6のいずれかに記載のデバイス。
- 上記ドリフト層(3)の上面に沿った横方向に、少なくとも3つ毎に配置された上記追加の層(7、7”)が、隣接するそれぞれの追加の層より大きな横方向の長さを有する請求項1〜6のいずれかに記載のデバイス。
- 上記それぞれの追加の層(7、7”)は、上記ドリフト層(3)の上に配置されて該ドリフト層に対して界面を形成し、かつ上記ショットキコンタクト領域(6)により横方向が限定され、
上記金属層領域は、該追加の層(7、7”)の、ドリフト層(3)とは反対側の面の上に配置され、かつ該追加の層(7、7”)の側面に接し、該追加の層(7、7”)の間を互いに分離する請求項1に記載のデバイス。
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US11/444,106 US7728403B2 (en) | 2006-05-31 | 2006-05-31 | Semiconductor device |
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PCT/SE2007/050342 WO2007139487A1 (en) | 2006-05-31 | 2007-05-22 | Schottky diode with incorporated pn- junctions |
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US7745845B2 (en) * | 2008-04-23 | 2010-06-29 | Fairchild Semiconductor Corporation | Integrated low leakage schottky diode |
US8232558B2 (en) * | 2008-05-21 | 2012-07-31 | Cree, Inc. | Junction barrier Schottky diodes with current surge capability |
JP5047133B2 (ja) * | 2008-11-19 | 2012-10-10 | 昭和電工株式会社 | 半導体装置の製造方法 |
JP5175872B2 (ja) * | 2010-01-21 | 2013-04-03 | 株式会社東芝 | 半導体整流装置 |
JP5607720B2 (ja) | 2010-02-23 | 2014-10-15 | 良孝 菅原 | 半導体装置 |
US9117739B2 (en) | 2010-03-08 | 2015-08-25 | Cree, Inc. | Semiconductor devices with heterojunction barrier regions and methods of fabricating same |
JP5172916B2 (ja) | 2010-09-08 | 2013-03-27 | 株式会社東芝 | 半導体整流装置 |
JP5377548B2 (ja) | 2011-03-03 | 2013-12-25 | 株式会社東芝 | 半導体整流装置 |
JP5306392B2 (ja) | 2011-03-03 | 2013-10-02 | 株式会社東芝 | 半導体整流装置 |
US8680587B2 (en) | 2011-09-11 | 2014-03-25 | Cree, Inc. | Schottky diode |
US8952481B2 (en) | 2012-11-20 | 2015-02-10 | Cree, Inc. | Super surge diodes |
JP6203074B2 (ja) * | 2014-02-17 | 2017-09-27 | 株式会社東芝 | 半導体装置およびその製造方法 |
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GB2131603B (en) * | 1982-12-03 | 1985-12-18 | Philips Electronic Associated | Semiconductor devices |
JPH04102373A (ja) * | 1990-08-22 | 1992-04-03 | Canon Inc | 半導体電子放出素子 |
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US5241195A (en) * | 1992-08-13 | 1993-08-31 | North Carolina State University At Raleigh | Merged P-I-N/Schottky power rectifier having extended P-I-N junction |
JPH0897441A (ja) * | 1994-09-26 | 1996-04-12 | Fuji Electric Co Ltd | 炭化けい素ショットキーダイオードの製造方法 |
US5719409A (en) * | 1996-06-06 | 1998-02-17 | Cree Research, Inc. | Silicon carbide metal-insulator semiconductor field effect transistor |
DE19723176C1 (de) * | 1997-06-03 | 1998-08-27 | Daimler Benz Ag | Leistungshalbleiter-Bauelement und Verfahren zu dessen Herstellung |
JP3581027B2 (ja) * | 1998-08-12 | 2004-10-27 | ローム株式会社 | ショットキーバリア半導体装置 |
JP4892787B2 (ja) * | 2001-04-09 | 2012-03-07 | 株式会社デンソー | ショットキーダイオード及びその製造方法 |
SE0101848D0 (sv) * | 2001-05-25 | 2001-05-25 | Abb Research Ltd | A method concerning a junction barrier Schottky diode, such a diode and use thereof |
US6524900B2 (en) * | 2001-07-25 | 2003-02-25 | Abb Research, Ltd | Method concerning a junction barrier Schottky diode, such a diode and use thereof |
FR2832547A1 (fr) * | 2001-11-21 | 2003-05-23 | St Microelectronics Sa | Procede de realisation d'une diode schottky sur substrat de carbure de silicium |
DE10259373B4 (de) * | 2002-12-18 | 2012-03-22 | Infineon Technologies Ag | Überstromfeste Schottkydiode mit niedrigem Sperrstrom |
US20050012143A1 (en) * | 2003-06-24 | 2005-01-20 | Hideaki Tanaka | Semiconductor device and method of manufacturing the same |
JP2005026408A (ja) * | 2003-07-01 | 2005-01-27 | Matsushita Electric Ind Co Ltd | 半導体素子およびその製造方法 |
US20060131686A1 (en) * | 2004-12-20 | 2006-06-22 | Silicon-Base Technology Corp. | LOCOS-based junction-pinched schottky rectifier and its manufacturing methods |
US7341932B2 (en) * | 2005-09-30 | 2008-03-11 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Schottky barrier diode and method thereof |
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US7728403B2 (en) | 2010-06-01 |
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