JP5676836B2 - エミッタ−ベーススペーサ領域中に低k材料を有するバイポーラトランジスタの作製方法 - Google Patents
エミッタ−ベーススペーサ領域中に低k材料を有するバイポーラトランジスタの作製方法 Download PDFInfo
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- JP5676836B2 JP5676836B2 JP2007187885A JP2007187885A JP5676836B2 JP 5676836 B2 JP5676836 B2 JP 5676836B2 JP 2007187885 A JP2007187885 A JP 2007187885A JP 2007187885 A JP2007187885 A JP 2007187885A JP 5676836 B2 JP5676836 B2 JP 5676836B2
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- 238000000034 method Methods 0.000 title claims description 15
- 239000000463 material Substances 0.000 title description 15
- 125000006850 spacer group Chemical group 0.000 title description 5
- 239000004065 semiconductor Substances 0.000 claims description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 230000000295 complement effect Effects 0.000 claims description 7
- 230000003071 parasitic effect Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 8
- 238000004891 communication Methods 0.000 description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 3
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- 229920000412 polyarylene Polymers 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 241000243321 Cnidaria Species 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000005441 aurora Substances 0.000 description 1
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- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Description
従来技術の上述の欠陥を解決するために、本発明は半導体ウエハ基板上に配置されたバイポーラトランジスタを実現する。一実施例において、バイポーラトランジスタは半導体ウエハ中に配置されたコレクタ、コレクタ中に配置されたベース、ベース中に配置され、ベースの少くとも一部と接触したエミッタを含み、エミッタはその中に低K層を有する。一実施例において、低K層はエミッタの側部に近接して配置される。しかし、低K層はエミッタの相対する側部に近接して配置するのが、なお好ましい。すべての実施例において、低K層はバイポーラトランジスタの適切な機能は妨げない。しかし、低K層は典型的な場合従来のバイポーラトランジスタに付随したエミッタ−ベース容量を本質的に減少させる。
本発明は、以下の図面を参照しつつ詳細な記述により最も理解される。半導体分野の標準的なプラクティスに従い、種々の要素は一定の比率に表されていない。実際、要素の寸法は解説のために任意に増減可能である。以下、図面との関連において本発明に関する言及がなされる。
110 バイポーラトランジスタ構造、バイポーラトランジスタ
115 コレクタ、コレクタタブ
117 ベース
120,125 相補金属−酸化物−半導体(CMOS)トランジスタ、CMOSトランジスタ
130 エミッタ
132 酸化物層、誘電体材料
134 高K層、誘電体材料
136 低誘電率(K)層、低K層、誘電体材料
138 誘電体層
200 半導体デバイス
210 CMOSトランジスタ
220 フィールド酸化物
230 酸化物層
240 CMOSゲート構造
250 高K層,層
260 低K層,層
310 誘電体層
320 開口
340 中がくぼんだ部分
410 エミッタポリ層,エミッタポリ
510 PETEOS堆積層
520 フォトレジストマスク
610 エミッタ
615 バイポーラトランジスタ
620 トランジスタゲート構造
630 ソース領域
640 ドレイン領域
650 スペーサ
710,810 フォトレジスト
Claims (10)
- 半導体ウエハ基板中に配置されたコレクタ;
コレクタ中に配置されたベース及び
ベースの上部表面上に直接配置され、ベースの少くとも一部と接触したエミッタを含み、前記エミッタは前記ベース上の高誘電率層と、当該高誘電率層上の3.9より低い誘電率を有する低誘電率層と、当該低誘電率層上に配置されたポリシリコン層又はアモルファスシリコン層とを有する半導体ウエハ基板上に配置されたバイポーラトランジスタ。 - バイポーラトランジスタに隣接して配置された相補金属−酸化物−半導体(CMOS)トランジスタデバイスが更に含まれ、バイポーラトランジスタ及びCMOSトランジスタデバイスは相互接続され、集積回路を形成する請求項1記載のバイポーラトランジスタ。
- 低誘電率層はエミッタの相対する側に近接して配置される請求項1記載のバイポーラトランジスタ。
- 前記高誘電率層は第1の高誘電率層と第2の高誘電率層を含む請求項1記載のバイポーラトランジスタ。
- 低誘電率層は3.8ないし2.1の範囲の誘電率を有する請求項1記載のバイポーラトランジスタ。
- 半導体ウエハ基板中にコレクタを形成する工程;
コレクタ中にベースを形成する工程;及び
ベースの上部表面上に直接配置し及びベースの少くとも一部と接触するエミッタを形成する工程を含み、前記エミッタは前記ベース上の高誘電率層と、当該高誘電率層上の3.9より低い誘電率を有する低誘電率層と、当該低誘電率層上に配置されたポリシリコン層又はアモルファスシリコン層とを有するバイポーラトランジスタの作製方法。 - バイポーラトランジスタに隣接して、相補金属−酸化物−半導体(CMOS)トランジスタデバイスを形成し、バイポーラトランジスタとCMOSトランジスタデバイスは相互接続され、集積回路を形成する工程を更に含む請求項6記載の方法。
- 前記高誘電率層は第1の高誘電率層と第2の高誘電率層を含む請求項6記載の方法。
- 低誘電率層の形成工程は、3.8ないし2.1の範囲の誘電率を有する低誘電率層を形成する工程を含む請求項6記載の方法。
- 低誘電率層が、低誘電率層の代わりに二酸化シリコン層を有するバイポーラトランジスタより、20%ないし30%小さい範囲のエミッタ−ベース容量と、低誘電率層の代わりに二酸化シリコン層を有するバイポーラトランジスタより少なくとも50%小さいエミッタ−ベース寄生容量を有するバイポーラトランジスタを供する請求項6記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/631,755 US6657281B1 (en) | 2000-08-03 | 2000-08-03 | Bipolar transistor with a low K material in emitter base spacer regions |
US09/631755 | 2000-08-03 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001236005A Division JP2002118116A (ja) | 2000-08-03 | 2001-08-03 | エミッタ−ベーススペーサ領域中に低k材料を有するバイポーラトランジスタの作製方法 |
Publications (2)
Publication Number | Publication Date |
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JP2007306025A JP2007306025A (ja) | 2007-11-22 |
JP5676836B2 true JP5676836B2 (ja) | 2015-02-25 |
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Family Applications (2)
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JP2001236005A Pending JP2002118116A (ja) | 2000-08-03 | 2001-08-03 | エミッタ−ベーススペーサ領域中に低k材料を有するバイポーラトランジスタの作製方法 |
JP2007187885A Expired - Fee Related JP5676836B2 (ja) | 2000-08-03 | 2007-07-19 | エミッタ−ベーススペーサ領域中に低k材料を有するバイポーラトランジスタの作製方法 |
Family Applications Before (1)
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JP2001236005A Pending JP2002118116A (ja) | 2000-08-03 | 2001-08-03 | エミッタ−ベーススペーサ領域中に低k材料を有するバイポーラトランジスタの作製方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6657281B1 (ja) |
EP (1) | EP1184907B1 (ja) |
JP (2) | JP2002118116A (ja) |
KR (1) | KR100439787B1 (ja) |
TW (1) | TW511290B (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US6657281B1 (en) * | 2000-08-03 | 2003-12-02 | Agere Systems Inc. | Bipolar transistor with a low K material in emitter base spacer regions |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS62206880A (ja) * | 1986-03-07 | 1987-09-11 | Nec Corp | ヘテロバイポ−ラトランジスタの製造方法 |
DE3825701A1 (de) | 1987-07-29 | 1989-02-09 | Toshiba Kawasaki Kk | Verfahren zur herstellung eines bipolaren transistors |
JPH01112770A (ja) * | 1987-10-27 | 1989-05-01 | Toshiba Corp | 半導体装置の製造方法 |
JPH01231369A (ja) * | 1988-03-11 | 1989-09-14 | Fujitsu Ltd | 半導体装置 |
JPH02152239A (ja) * | 1988-12-05 | 1990-06-12 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置の製造方法 |
US5204276A (en) | 1988-12-06 | 1993-04-20 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
JPH02205033A (ja) * | 1989-02-03 | 1990-08-14 | Hitachi Ltd | バイポーラトランジスタおよびその製造方法 |
US5073810A (en) | 1989-11-07 | 1991-12-17 | Hitachi, Ltd. | Semiconductor integrated circuit device and manufacturing method thereof |
US5087580A (en) * | 1990-09-17 | 1992-02-11 | Texas Instruments Incorporated | Self-aligned bipolar transistor structure and fabrication process |
US5102809A (en) * | 1990-10-11 | 1992-04-07 | Texas Instruments Incorporated | SOI BICMOS process |
JP3307489B2 (ja) * | 1993-12-09 | 2002-07-24 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP2803548B2 (ja) * | 1993-12-28 | 1998-09-24 | 日本電気株式会社 | 半導体装置の製造方法 |
US6239477B1 (en) * | 1998-10-07 | 2001-05-29 | Texas Instruments Incorporated | Self-aligned transistor contact for epitaxial layers |
JP2000156382A (ja) * | 1998-11-19 | 2000-06-06 | Nec Corp | 半導体装置及びその製造方法 |
US6531369B1 (en) * | 2000-03-01 | 2003-03-11 | Applied Micro Circuits Corporation | Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe) |
US6414371B1 (en) * | 2000-05-30 | 2002-07-02 | International Business Machines Corporation | Process and structure for 50+ gigahertz transistor |
US6657281B1 (en) * | 2000-08-03 | 2003-12-02 | Agere Systems Inc. | Bipolar transistor with a low K material in emitter base spacer regions |
-
2000
- 2000-08-03 US US09/631,755 patent/US6657281B1/en not_active Expired - Fee Related
-
2001
- 2001-07-28 KR KR10-2001-0045662A patent/KR100439787B1/ko not_active IP Right Cessation
- 2001-08-01 EP EP01306612A patent/EP1184907B1/en not_active Expired - Lifetime
- 2001-08-02 TW TW090118908A patent/TW511290B/zh not_active IP Right Cessation
- 2001-08-03 JP JP2001236005A patent/JP2002118116A/ja active Pending
-
2007
- 2007-07-19 JP JP2007187885A patent/JP5676836B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
TW511290B (en) | 2002-11-21 |
KR20020011873A (ko) | 2002-02-09 |
US6657281B1 (en) | 2003-12-02 |
KR100439787B1 (ko) | 2004-07-12 |
JP2007306025A (ja) | 2007-11-22 |
EP1184907A1 (en) | 2002-03-06 |
EP1184907B1 (en) | 2008-04-23 |
JP2002118116A (ja) | 2002-04-19 |
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