JP4378283B2 - 自己整合バイポーラトランジスタおよび関連の構造を製造するための方法 - Google Patents
自己整合バイポーラトランジスタおよび関連の構造を製造するための方法 Download PDFInfo
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- JP4378283B2 JP4378283B2 JP2004527591A JP2004527591A JP4378283B2 JP 4378283 B2 JP4378283 B2 JP 4378283B2 JP 2004527591 A JP2004527591 A JP 2004527591A JP 2004527591 A JP2004527591 A JP 2004527591A JP 4378283 B2 JP4378283 B2 JP 4378283B2
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- 239000011368 organic material Substances 0.000 claims description 9
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical group [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 claims description 3
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 229910052717 sulfur Inorganic materials 0.000 claims description 2
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- 238000001039 wet etching Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 80
- 238000010586 diagram Methods 0.000 description 28
- 239000000463 material Substances 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
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- 238000002955 isolation Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000012544 monitoring process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
- H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Description
Transistor”)」と題された係属中の関連の米国特許出願を、これにより引用により完全に援用する。
の制御において一部の正確さが失われるというさらなる問題をもたらす。
ランジスタにおける自己整合エミッタを製造するための方法」と題された係属中の関連の米国特許出願に開示されている。同時継続出願における開示は、これによりこの出願に引用により完全に援用される。
なエミッタウインドウ開口の幅を与えることによって、本発明は犠牲ポスト302の上で事実上自己整合するエミッタウインドウ開口を達成する。一実施例において、犠牲ポスト302を覆う犠牲平坦化層324の厚さ328は、マスク330が必要でないように適切な厚さに減じることができる。このような実施例において、厚さ328はたとえば、約10.0オングストロームまたはそれ未満であるかもしれない。したがって、犠牲ポスト302にわたって位置する薄い犠牲平坦化層324は後に続くエッチングステップにおいて最初にエッチングされるため、結果として生じるエミッタウインドウ開口が犠牲ポスト302の上で自己整合される。すなわち、犠牲ポスト302の上でエミッタウインドウ開口を位置合わせするのにマスクは必要とされない。図3Bを参照すると、フロー図200のステップ278の結果が構造378によって示されている。
ーサ314および316の上部を平坦化する。次に、エミッタ342は、エミッタウインドウ開口332におけるベース320の上面326に多結晶材料を堆積することによって形成される。一実施例において、エミッタ342はNタイプの多結晶シリコンを含む。エミッタ342のエミッタ幅344は、図3Aの犠牲ポストの幅308に実質的に等しい。さらに、エミッタ342は、リンクスペーサ314および316によって、外部ベース領域312に自己整合される。エミッタ342をパターニングし、コンタクトを形成する後に続くステップおよび他のステップは、当該技術で周知のように行なうことができる。
Claims (10)
- バイポーラトランジスタを製造するための方法であって、前記方法は、
ベースの上面に犠牲ポストを製造するステップと、
前記犠牲ポストの第1のおよび第2の側に、第1のおよび第2のリンクスペーサをそれぞれ製造するステップと、
前記犠牲ポスト、前記第1および第2のリンクスペーサ、および前記ベースにわたって、誘電体を含むコンフォーマルな層を形成するステップと、
犠牲平坦化層が前記第1および第2のリンクスペーサの間の第1の領域において第1の厚さを有し、かつ前記第1および第2のリンクスペーサの外側の第2の領域において第2の厚さを有するように、前記コンフォーマルな層にわたって前記犠牲平坦化層を堆積するステップと、
前記犠牲平坦化層の上にマスクを堆積するステップと、
前記マスクにエミッタウインドウ開口をパターニングするステップとを含み、
前記エミッタウインドウ開口内の前記犠牲平坦化層を除去するステップと、
前記犠牲ポストを除去し、それによってエミッタを形成するための領域を形成するステップと、
前記第2の厚さを前記第1の厚さよりも大きくすることにより、位置合わせ不良の誤差の許容誤差を増大させて前記エミッタウインドウ開口が前記犠牲ポストの上で自己整合するように前記エミッタウインドウ開口の幅を増大させる、方法。 - 前記犠牲平坦化層は有機材料を含む、請求項1に記載の方法。
- プラズマエッチングおよび硫黄ウエットエッチングからなるグループから選択されたプロセスによって、前記犠牲平坦化層を除去する、請求項2に記載の方法。
- 前記有機材料は有機BARCである、請求項2に記載の方法。
- 前記犠牲平坦化層は、スピンプロセスを用いて堆積される、請求項1に記載の方法。
- 前記エミッタウインドウ開口の幅は、前記犠牲ポストの幅よりも広い、請求項1に記載の方法。
- 前記エミッタウインドウ開口の幅は、前記第1および第2のリンクスペーサのそれぞれの外側縁部の間の距離よりも狭い、請求項1に記載の方法。
- 前記犠牲平坦化層を前記エミッタウインドウ開口において除去する工程は、前記コンフォーマルな層を露出し、かつ前記エミッタウインドウ開口を拡張する、請求項1に記載の方法。
- 前記バイポーラトランジスタは、シリコン・ゲルマニウム・ヘテロ接合バイポーラトランジスタである、請求項1に記載の方法。
- 前記バイポーラトランジスタは、シリコン・ゲルマニウム・カーボンヘテロ接合バイポーラトランジスタである、請求項1に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/218,527 US6784467B1 (en) | 2002-08-13 | 2002-08-13 | Method for fabricating a self-aligned bipolar transistor and related structure |
PCT/US2003/021193 WO2004015755A1 (en) | 2002-08-13 | 2003-07-03 | Method for fabricating a self-aligned bipolar transistor and related structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006505922A JP2006505922A (ja) | 2006-02-16 |
JP4378283B2 true JP4378283B2 (ja) | 2009-12-02 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2004527591A Expired - Fee Related JP4378283B2 (ja) | 2002-08-13 | 2003-07-03 | 自己整合バイポーラトランジスタおよび関連の構造を製造するための方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US6784467B1 (ja) |
EP (1) | EP1535322A4 (ja) |
JP (1) | JP4378283B2 (ja) |
CN (1) | CN100487875C (ja) |
HK (1) | HK1083041A1 (ja) |
TW (1) | TWI229388B (ja) |
WO (1) | WO2004015755A1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7064415B1 (en) * | 2002-08-13 | 2006-06-20 | Newport Fab Llc | Self-aligned bipolar transistor having increased manufacturability |
US6867440B1 (en) * | 2002-08-13 | 2005-03-15 | Newport Fab, Llc | Self-aligned bipolar transistor without spacers and method for fabricating same |
FR2858877B1 (fr) * | 2003-08-11 | 2005-10-21 | St Microelectronics Sa | Transistor bipolaire a heterojonction |
US7375410B2 (en) | 2004-02-25 | 2008-05-20 | International Business Machines Corporation | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof |
DE102004021241A1 (de) * | 2004-04-30 | 2005-11-17 | Infineon Technologies Ag | Verfahren zur Herstellung eines planaren Spacers, eines zugehörigen Bipolartransistors und einer zugehörigen BiCMOS-Schaltungsanordnung |
US7288829B2 (en) * | 2004-11-10 | 2007-10-30 | International Business Machines Corporation | Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide |
US7709338B2 (en) * | 2006-12-21 | 2010-05-04 | International Business Machines Corporation | BiCMOS devices with a self-aligned emitter and methods of fabricating such BiCMOS devices |
CN100580898C (zh) * | 2007-11-28 | 2010-01-13 | 中国科学院微电子研究所 | 一种引出亚微米hbt发射极/hemt栅的方法 |
JP5545827B2 (ja) * | 2010-03-25 | 2014-07-09 | 旭化成エレクトロニクス株式会社 | シリコンゲルマニウムトランジスタの製造方法 |
US8492237B2 (en) | 2011-03-08 | 2013-07-23 | International Business Machines Corporation | Methods of fabricating a bipolar junction transistor with a self-aligned emitter and base |
US9252217B2 (en) * | 2014-05-29 | 2016-02-02 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement and formation thereof |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2569058B2 (ja) | 1987-07-10 | 1997-01-08 | 株式会社日立製作所 | 半導体装置 |
DE59005820D1 (de) | 1990-01-08 | 1994-06-30 | Siemens Ag | Verfahren zur Herstellung eines selbstjustierten Emitter-Basis-Komplexes. |
NL9100062A (nl) | 1991-01-14 | 1992-08-03 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting. |
US5451532A (en) * | 1994-03-15 | 1995-09-19 | National Semiconductor Corp. | Process for making self-aligned polysilicon base contact in a bipolar junction transistor |
US6020246A (en) * | 1998-03-13 | 2000-02-01 | National Semiconductor Corporation | Forming a self-aligned epitaxial base bipolar transistor |
FR2778022B1 (fr) * | 1998-04-22 | 2001-07-13 | France Telecom | Transistor bibolaire vertical, en particulier a base a heterojonction sige, et procede de fabrication |
FR2804247B1 (fr) | 2000-01-21 | 2002-04-12 | St Microelectronics Sa | Procede de realisation d'un transistor bipolaire a emetteur et base extrinseque auto-alignes |
US6620732B1 (en) * | 2000-11-17 | 2003-09-16 | Newport Fab, Llc | Method for controlling critical dimension in a polycrystalline silicon emitter and related structure |
US6534372B1 (en) * | 2000-11-22 | 2003-03-18 | Newport Fab, Llc | Method for fabricating a self-aligned emitter in a bipolar transistor |
-
2002
- 2002-08-13 US US10/218,527 patent/US6784467B1/en not_active Expired - Lifetime
-
2003
- 2003-07-03 EP EP03784755A patent/EP1535322A4/en not_active Withdrawn
- 2003-07-03 CN CNB038194406A patent/CN100487875C/zh not_active Expired - Fee Related
- 2003-07-03 JP JP2004527591A patent/JP4378283B2/ja not_active Expired - Fee Related
- 2003-07-03 WO PCT/US2003/021193 patent/WO2004015755A1/en active Application Filing
- 2003-07-31 TW TW092121031A patent/TWI229388B/zh not_active IP Right Cessation
-
2004
- 2004-06-17 US US10/870,900 patent/US7041564B1/en not_active Expired - Lifetime
-
2006
- 2006-03-09 HK HK06103048.0A patent/HK1083041A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US6784467B1 (en) | 2004-08-31 |
WO2004015755A1 (en) | 2004-02-19 |
EP1535322A4 (en) | 2008-07-23 |
CN1714435A (zh) | 2005-12-28 |
CN100487875C (zh) | 2009-05-13 |
US7041564B1 (en) | 2006-05-09 |
HK1083041A1 (en) | 2006-06-23 |
TW200405477A (en) | 2004-04-01 |
TWI229388B (en) | 2005-03-11 |
JP2006505922A (ja) | 2006-02-16 |
WO2004015755B1 (en) | 2005-11-10 |
EP1535322A1 (en) | 2005-06-01 |
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LAPS | Cancellation because of no payment of annual fees |