JP5669752B2 - チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減 - Google Patents

チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減 Download PDF

Info

Publication number
JP5669752B2
JP5669752B2 JP2011542725A JP2011542725A JP5669752B2 JP 5669752 B2 JP5669752 B2 JP 5669752B2 JP 2011542725 A JP2011542725 A JP 2011542725A JP 2011542725 A JP2011542725 A JP 2011542725A JP 5669752 B2 JP5669752 B2 JP 5669752B2
Authority
JP
Japan
Prior art keywords
silicon
forming
semiconductor
layer
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2011542725A
Other languages
English (en)
Japanese (ja)
Other versions
JP2012514318A5 (cg-RX-API-DMAC7.html
JP2012514318A (ja
Inventor
クロンホルツ ステファン
クロンホルツ ステファン
オットー アンドレア
オットー アンドレア
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2012514318A publication Critical patent/JP2012514318A/ja
Publication of JP2012514318A5 publication Critical patent/JP2012514318A5/ja
Application granted granted Critical
Publication of JP5669752B2 publication Critical patent/JP5669752B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/014—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
JP2011542725A 2008-12-31 2009-12-29 チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減 Active JP5669752B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102008063402A DE102008063402B4 (de) 2008-12-31 2008-12-31 Verringerung der Schwellwertspannungsfluktuation in Transistoren mit einer Kanalhalbleiterlegierung durch Verringern der Abscheideungleichmäßigkeiten
DE102008063402.6 2008-12-31
US12/637,112 2009-12-14
US12/637,112 US8236654B2 (en) 2008-12-31 2009-12-14 Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities
PCT/EP2009/009307 WO2010076018A1 (en) 2008-12-31 2009-12-29 Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities

Publications (3)

Publication Number Publication Date
JP2012514318A JP2012514318A (ja) 2012-06-21
JP2012514318A5 JP2012514318A5 (cg-RX-API-DMAC7.html) 2013-02-07
JP5669752B2 true JP5669752B2 (ja) 2015-02-18

Family

ID=42234616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011542725A Active JP5669752B2 (ja) 2008-12-31 2009-12-29 チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減

Country Status (6)

Country Link
US (1) US8236654B2 (cg-RX-API-DMAC7.html)
JP (1) JP5669752B2 (cg-RX-API-DMAC7.html)
KR (1) KR101539416B1 (cg-RX-API-DMAC7.html)
CN (1) CN102341906B (cg-RX-API-DMAC7.html)
DE (1) DE102008063402B4 (cg-RX-API-DMAC7.html)
WO (1) WO2010076018A1 (cg-RX-API-DMAC7.html)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009006886B4 (de) 2009-01-30 2012-12-06 Advanced Micro Devices, Inc. Verringerung von Dickenschwankungen einer schwellwerteinstellenden Halbleiterlegierung durch Verringern der Strukturierungsungleichmäßigkeiten vor dem Abscheiden der Halbleiterlegierung
JP5605134B2 (ja) * 2010-09-30 2014-10-15 富士通セミコンダクター株式会社 半導体装置及びその製造方法
DE102010063296B4 (de) * 2010-12-16 2012-08-16 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Herstellungsverfahren mit reduzierter STI-Topograpie für Halbleiterbauelemente mit einer Kanalhalbleiterlegierung
US8609509B2 (en) * 2011-09-22 2013-12-17 Globalfoundries Inc. Superior integrity of high-k metal gate stacks by forming STI regions after gate metals
US8377773B1 (en) * 2011-10-31 2013-02-19 Globalfoundries Inc. Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask
US8541281B1 (en) 2012-08-17 2013-09-24 Globalfoundries Inc. Replacement gate process flow for highly scaled semiconductor devices
US8969190B2 (en) 2012-08-24 2015-03-03 Globalfoundries Inc. Methods of forming a layer of silicon on a layer of silicon/germanium
US9029919B2 (en) 2013-02-01 2015-05-12 Globalfoundries Inc. Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69609313T2 (de) * 1995-12-15 2001-02-01 Koninklijke Philips Electronics N.V., Eindhoven Halbleiterfeldeffektanordnung mit einer sige schicht
JP2000353753A (ja) * 1999-06-14 2000-12-19 Hitachi Ltd 半導体装置の製造方法
EP1421607A2 (en) * 2001-02-12 2004-05-26 ASM America, Inc. Improved process for deposition of semiconductor films
WO2002082514A1 (en) * 2001-04-04 2002-10-17 Massachusetts Institute Of Technology A method for semiconductor device fabrication
JP2004006959A (ja) * 2001-04-12 2004-01-08 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US6794252B2 (en) * 2001-09-28 2004-09-21 Texas Instruments Incorporated Method and system for forming dual work function gate electrodes in a semiconductor device
US6600170B1 (en) * 2001-12-17 2003-07-29 Advanced Micro Devices, Inc. CMOS with strained silicon channel NMOS and silicon germanium channel PMOS
AU2002357376A1 (en) * 2002-03-28 2003-10-13 Advanced Micro Devices, Inc. Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same
KR100487525B1 (ko) * 2002-04-25 2005-05-03 삼성전자주식회사 실리콘게르마늄 게이트를 이용한 반도체 소자 및 그 제조방법
JP2003332458A (ja) * 2002-05-09 2003-11-21 Fujitsu Ltd 半導体装置及びその製造方法
KR20030090411A (ko) * 2002-05-23 2003-11-28 삼성전자주식회사 선택적 성장을 이용한 씨모스 게이트 및 그 제조방법
CN100483666C (zh) * 2003-01-07 2009-04-29 S.O.I.Tec绝缘体上硅技术公司 施主晶片以及重复利用晶片的方法和剥离有用层的方法
US6828181B2 (en) * 2003-05-08 2004-12-07 International Business Machines Corporation Dual gate material process for CMOS technologies
JP4322255B2 (ja) * 2003-08-05 2009-08-26 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
US7223679B2 (en) * 2003-12-24 2007-05-29 Intel Corporation Transistor gate electrode having conductor material layer
EP1748482A1 (en) * 2004-04-30 2007-01-31 Matsushita Electric Industrial Co., Ltd. Semiconductor manufacturing method and semiconductor device
KR101292435B1 (ko) * 2004-09-14 2013-07-31 아리조나 보드 오브 리전트스, 아리조나주의 아리조나 주립대 대행법인 기판상의 Ｓｉ-Ｇｅ 반도체 소재 및 소자의 성장 방법
JP2006108251A (ja) * 2004-10-01 2006-04-20 Rohm Co Ltd 半導体装置の製造方法
JP2006202928A (ja) * 2005-01-19 2006-08-03 Nec Electronics Corp 半導体装置の製造方法
US7132322B1 (en) * 2005-05-11 2006-11-07 International Business Machines Corporation Method for forming a SiGe or SiGeC gate selectively in a complementary MIS/MOS FET device
TWI267926B (en) * 2005-09-23 2006-12-01 Ind Tech Res Inst A new method for high mobility enhancement strained channel CMOS with single workfunction metal-gate
JP4795817B2 (ja) * 2006-03-02 2011-10-19 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2006332687A (ja) * 2006-07-10 2006-12-07 Fujitsu Ltd Ｃｍｏｓ半導体装置
KR100809327B1 (ko) * 2006-08-10 2008-03-05 삼성전자주식회사 반도체 소자 및 그 제조방법
US7750374B2 (en) * 2006-11-14 2010-07-06 Freescale Semiconductor, Inc Process for forming an electronic device including a transistor having a metal gate electrode
KR100773359B1 (ko) * 2006-11-20 2007-11-05 삼성전자주식회사 높은 이동도를 갖는 트랜지스터들의 제조방법 및 그에 의해제조된 트랜지스터들
US7598142B2 (en) * 2007-03-15 2009-10-06 Pushkar Ranade CMOS device with dual-epi channels and self-aligned contacts
JP4898517B2 (ja) * 2007-03-27 2012-03-14 シャープ株式会社 半導体装置の製造方法
US7709331B2 (en) * 2007-09-07 2010-05-04 Freescale Semiconductor, Inc. Dual gate oxide device integration
US20090108294A1 (en) * 2007-10-30 2009-04-30 International Business Machines Corporation Scalable high-k dielectric gate stack
US7718496B2 (en) * 2007-10-30 2010-05-18 International Business Machines Corporation Techniques for enabling multiple Vt devices using high-K metal gate stacks
US8053306B2 (en) * 2007-12-13 2011-11-08 International Business Machines Corporation PFET with tailored dielectric and related methods and integrated circuit
JP2010157570A (ja) * 2008-12-26 2010-07-15 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US8236654B2 (en) 2012-08-07
CN102341906A (zh) 2012-02-01
KR20120067973A (ko) 2012-06-26
DE102008063402B4 (de) 2013-10-17
WO2010076018A1 (en) 2010-07-08
US20100164014A1 (en) 2010-07-01
JP2012514318A (ja) 2012-06-21
KR101539416B1 (ko) 2015-07-27
CN102341906B (zh) 2014-10-15
DE102008063402A1 (de) 2010-07-08

Similar Documents

Publication Publication Date Title
JP5781944B2 (ja) スレッショルド調節半導体合金を堆積させるのに先立ちパターニング不均一性を低減することによる前記半導体合金の厚みばらつきの低減
TWI438867B (zh) 具不同型式與厚度的閘極絕緣層之ｃｍｏｓ裝置及其形成方法
US8343837B2 (en) Work function adjustment in a high-k gate electrode structure after transistor fabrication by using lanthanum
US8329549B2 (en) Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure
US20100244141A1 (en) Threshold adjustment of transistors including high-k metal gate electrode structures comprising an intermediate etch stop layer
US8349694B2 (en) Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy
US8378432B2 (en) Maintaining integrity of a high-K gate stack by an offset spacer used to determine an offset of a strain-inducing semiconductor alloy
CN102446729B (zh) 用湿式化学方法形成受控底切而有优异完整性的高介电系数栅极堆栈
JP5669752B2 (ja) チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減
US20100330757A1 (en) Enhanced cap layer integrity in a high-k metal gate stack by using a hard mask for offset spacer patterning
US20120211838A1 (en) Complementary Transistors Comprising High-K Metal Gate Electrode Structures and Epitaxially Formed Semiconductor Materials in the Drain and Source Areas
US20130115773A1 (en) Prevention of ILD Loss in Replacement Gate Technologies by Surface Treatmen
US20110049585A1 (en) Maintaining integrity of a high-k gate stack by passivation using an oxygen plasma
US8324091B2 (en) Enhancing integrity of a high-k gate stack by confining a metal cap layer after deposition
US8513080B2 (en) Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device
US8377773B1 (en) Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask
WO2010086152A1 (en) Reduction of thickness variations of a threshold adjusting semiconductor alloy by reducing patterning non-uniformities prior to depositing the semiconductor alloy

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121212

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20121212

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140226

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140228

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140526

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140813

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141105

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20141202

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141216

R150 Certificate of patent or registration of utility model

Ref document number: 5669752

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250