JP5661990B2 - Ｓｏｉ基板の製造方法 - Google Patents

Ｓｏｉ基板の製造方法 Download PDF

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Publication number
JP5661990B2
JP5661990B2 JP2008109391A JP2008109391A JP5661990B2 JP 5661990 B2 JP5661990 B2 JP 5661990B2 JP 2008109391 A JP2008109391 A JP 2008109391A JP 2008109391 A JP2008109391 A JP 2008109391A JP 5661990 B2 JP5661990 B2 JP 5661990B2
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Japan
Prior art keywords
substrate
layer
heat treatment
single crystal
ions
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Expired - Fee Related
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JP2008109391A
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English (en)
Japanese (ja)
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JP2008288579A (ja
JP2008288579A5 (enExample
Inventor
大沼　英人
英人 大沼
陽一 飯窪
陽一 飯窪
崇佳 佐藤
崇佳 佐藤
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008109391A priority Critical patent/JP5661990B2/ja
Publication of JP2008288579A publication Critical patent/JP2008288579A/ja
Publication of JP2008288579A5 publication Critical patent/JP2008288579A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
JP2008109391A 2007-04-20 2008-04-18 Ｓｏｉ基板の製造方法 Expired - Fee Related JP5661990B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008109391A JP5661990B2 (ja) 2007-04-20 2008-04-18 Ｓｏｉ基板の製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007112432 2007-04-20
JP2007112432 2007-04-20
JP2008109391A JP5661990B2 (ja) 2007-04-20 2008-04-18 Ｓｏｉ基板の製造方法

Publications (3)

Publication Number Publication Date
JP2008288579A JP2008288579A (ja) 2008-11-27
JP2008288579A5 JP2008288579A5 (enExample) 2011-05-19
JP5661990B2 true JP5661990B2 (ja) 2015-01-28

Family

ID=40132736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008109391A Expired - Fee Related JP5661990B2 (ja) 2007-04-20 2008-04-18 Ｓｏｉ基板の製造方法

Country Status (2)

Country Link
US (2) US7767542B2 (enExample)
JP (1) JP5661990B2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5459899B2 (ja) * 2007-06-01 2014-04-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
FR2926674B1 (fr) 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
US7939389B2 (en) 2008-04-18 2011-05-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5391599B2 (ja) * 2008-07-14 2014-01-15 オムロン株式会社 基板接合方法及び電子部品
US8815657B2 (en) * 2008-09-05 2014-08-26 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
JP2010239123A (ja) * 2009-03-12 2010-10-21 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
JP5658916B2 (ja) * 2009-06-26 2015-01-28 株式会社半導体エネルギー研究所 半導体装置
JP2011029610A (ja) * 2009-06-26 2011-02-10 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
JP5866088B2 (ja) * 2009-11-24 2016-02-17 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US8288249B2 (en) * 2010-01-26 2012-10-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8735263B2 (en) 2011-01-21 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP6056516B2 (ja) * 2013-02-01 2017-01-11 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
FR3007891B1 (fr) * 2013-06-28 2016-11-25 Soitec Silicon On Insulator Procede de fabrication d'une structure composite
US9768109B2 (en) 2015-09-22 2017-09-19 Qualcomm Incorporated Integrated circuits (ICS) on a glass substrate
US9725312B1 (en) * 2016-02-05 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Preconditioning to enhance hydrophilic fusion bonding

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2753955B2 (ja) * 1993-07-31 1998-05-20 株式会社半導体エネルギー研究所 ガラス基板処理方法
JPH11163363A (ja) * 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP4653374B2 (ja) * 2001-08-23 2011-03-16 セイコーエプソン株式会社 電気光学装置の製造方法
US7119365B2 (en) 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
JP4772258B2 (ja) 2002-08-23 2011-09-14 シャープ株式会社 Ｓｏｉ基板の製造方法
JP2004134675A (ja) 2002-10-11 2004-04-30 Sharp Corp Ｓｏｉ基板、表示装置およびｓｏｉ基板の製造方法
US7508034B2 (en) 2002-09-25 2009-03-24 Sharp Kabushiki Kaisha Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device
JP2004335642A (ja) * 2003-05-06 2004-11-25 Canon Inc 基板およびその製造方法
JP5110772B2 (ja) 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
JP2006210899A (ja) * 2004-12-28 2006-08-10 Shin Etsu Chem Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウェーハ
KR101436116B1 (ko) * 2007-04-27 2014-09-01 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판 및 그 제조 방법, 및 반도체 장치

Also Published As

Publication number Publication date
US20100270639A1 (en) 2010-10-28
US20080311726A1 (en) 2008-12-18
US7955949B2 (en) 2011-06-07
JP2008288579A (ja) 2008-11-27
US7767542B2 (en) 2010-08-03

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