JP5624081B2 - 三次元集積回路 - Google Patents
三次元集積回路 Download PDFInfo
- Publication number
- JP5624081B2 JP5624081B2 JP2012116245A JP2012116245A JP5624081B2 JP 5624081 B2 JP5624081 B2 JP 5624081B2 JP 2012116245 A JP2012116245 A JP 2012116245A JP 2012116245 A JP2012116245 A JP 2012116245A JP 5624081 B2 JP5624081 B2 JP 5624081B2
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- Prior art keywords
- conductive pattern
- wafer
- metal
- conductive
- directional
- Prior art date
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- 239000002184 metal Substances 0.000 claims description 108
- 238000006073 displacement reaction Methods 0.000 claims description 43
- 230000010354 integration Effects 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 93
- 238000010586 diagram Methods 0.000 description 27
- 238000005259 measurement Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 6
- 241000724291 Tobacco streak virus Species 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 241000287463 Phalacrocorax Species 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0614—Circular array, i.e. array with radial symmetry
- H01L2224/06144—Circular array, i.e. array with radial symmetry covering only portions of the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Automation & Control Theory (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
RC3L=RW−4×r
RC3D=RW−2×r
110、110’、110” 第1ウェハ
112、112’、112” 第1導電パターン
112U、112D、112L、112R、112U’、112D’、112L’、112R’ 方向導電パターン
113、113’ ドープ領域
114、114’、114” 第3導電パターン
116、116’、116” TSV
120、120’、120” 第2ウェハ
122、122’、122” 第2導電パターン
S1、S3 第1ウェハの表面
S2 第2ウェハの表面
C1、C2、C3、C4 中央導電パターン
ML 金属線
W 金属線の線幅
T1〜T5、B1〜B5、R1〜R5、L1〜L5、L、R、U、D、Y1〜Y2、I1〜I2 金属パッド
Claims (3)
- 第1導電パターンを含む第1ウェハと、
第2導電パターンを含み、前記第1導電パターンに電気接続された第2ウェハと
を含み、
前記第1ウェハと前記第2ウェハの間の変位が、前記第1導電パターンと前記第2導電パターンの抵抗に基づいて決定され、
前記第1導電パターンが、
前記第2導電パターンに電気接続されうる第1中央導電パターンと、
前記第1中央導電パターンを取り囲むように前記第1中央導電パターンの上下左右に配置されると共に、少なくとも1つが前記第2導電パターンに電気接続されうる複数の方向導電パターンと
を含み、
異なる方向の前記第1ウェハと前記第2ウェハの変位が、前記第1中央導電パターン、前記対応する方向導電パターンおよび前記第2導電パターンの抵抗に基づいて決定され、
前記各方向導電パターンが、
金属パッドと、
ドープ領域と、
前記ドープ領域を介して前記金属パッドに電気接続された複数の金属線と
を含み、
前記第1導電パターンと前記第2導電パターンの前記抵抗が、少なくとも、前記第2導電パターンによって短絡した前記金属線の数および前記短絡した金属線の線間抵抗に基づいて決定される三次元集積回路。 - 前記第2導電パターンが、
前記第1導電パターンに電気接続されうる第2中央導電パターン
を含み、
前記異なる方向の前記第1ウェハと前記第2ウェハの変位が、前記第1中央導電パターン、前記対応する方向導電パターンおよび前記第2中央導電パターンの抵抗に基づいて決定される請求項1に記載の三次元集積回路。 - 前記第1導電パターンが、
前記第2導電パターンに電気接続されうる複数の方向導電パターン
を含み、
特定方向の前記第1ウェハと前記第2ウェハの変位が、前記方向導電パターンおよび前記第2導電パターンの抵抗に基づいて決定される請求項1又は2に記載の三次元集積回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100132705 | 2011-09-09 | ||
TW100132705A TWI443803B (zh) | 2011-09-09 | 2011-09-09 | 三維積體電路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013058732A JP2013058732A (ja) | 2013-03-28 |
JP5624081B2 true JP5624081B2 (ja) | 2014-11-12 |
Family
ID=47829125
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012116245A Active JP5624081B2 (ja) | 2011-09-09 | 2012-05-22 | 三次元集積回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8546952B2 (ja) |
JP (1) | JP5624081B2 (ja) |
KR (1) | KR101373267B1 (ja) |
TW (1) | TWI443803B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112309882B (zh) * | 2020-09-21 | 2022-06-07 | 中国电子科技集团公司第十三研究所 | 三维集成器件焊接可靠性试验方法及监测系统 |
US20230349729A1 (en) * | 2022-04-28 | 2023-11-02 | Texas Instruments Incorporated | Resistive differential alignment monitor |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4571538A (en) | 1983-04-25 | 1986-02-18 | Rockwell International Corporation | Mask alignment measurement structure for semiconductor fabrication |
US6380554B1 (en) * | 1998-06-08 | 2002-04-30 | Advanced Micro Devices, Inc. | Test structure for electrically measuring the degree of misalignment between successive layers of conductors |
KR100273317B1 (ko) * | 1998-11-04 | 2000-12-15 | 김영환 | 반도체 소자 제조 공정에서 미스얼라이먼트 측정을 위한 테스트패턴의 구조와 그 측정방법 |
JP3306505B2 (ja) * | 1999-07-15 | 2002-07-24 | 独立行政法人産業技術総合研究所 | フリップチップ接続アライメント精度評価方法 |
US6383827B1 (en) * | 2000-04-17 | 2002-05-07 | Advanced Micro Devices, Inc. | Electrical alignment test structure using local interconnect ladder resistor |
TW477019B (en) * | 2000-09-15 | 2002-02-21 | Promos Technologies Inc | Via chain structure and process with testing potential |
JP4401070B2 (ja) * | 2002-02-05 | 2010-01-20 | ソニー株式会社 | 半導体装置内蔵多層配線基板及びその製造方法 |
US7354798B2 (en) | 2002-12-20 | 2008-04-08 | International Business Machines Corporation | Three-dimensional device fabrication method |
KR100575619B1 (ko) * | 2003-10-08 | 2006-05-03 | 매그나칩 반도체 유한회사 | 테스트 패턴 |
JP2005340696A (ja) * | 2004-05-31 | 2005-12-08 | Nec Yamaguchi Ltd | プローブ針の位置検出方法、半導体装置および半導体検査装置 |
KR100621960B1 (ko) * | 2005-05-19 | 2006-09-08 | 인터내셔널 비지네스 머신즈 코포레이션 | 3차원 디바이스 제조 방법 |
US7598523B2 (en) * | 2007-03-19 | 2009-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test structures for stacking dies having through-silicon vias |
US7528492B2 (en) * | 2007-05-24 | 2009-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test patterns for detecting misalignment of through-wafer vias |
US7514276B1 (en) * | 2008-08-12 | 2009-04-07 | International Business Machines Corporation | Aligning stacked chips using resistance assistance |
JP2010087273A (ja) * | 2008-09-30 | 2010-04-15 | Panasonic Corp | 電子デバイス及びその製造方法 |
US8343781B2 (en) * | 2010-09-21 | 2013-01-01 | International Business Machines Corporation | Electrical mask inspection |
-
2011
- 2011-09-09 TW TW100132705A patent/TWI443803B/zh active
- 2011-11-10 KR KR1020110116853A patent/KR101373267B1/ko active IP Right Grant
- 2011-11-11 US US13/294,183 patent/US8546952B2/en active Active
-
2012
- 2012-05-22 JP JP2012116245A patent/JP5624081B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
TW201312724A (zh) | 2013-03-16 |
JP2013058732A (ja) | 2013-03-28 |
KR20130028609A (ko) | 2013-03-19 |
TWI443803B (zh) | 2014-07-01 |
KR101373267B1 (ko) | 2014-03-11 |
US20130062776A1 (en) | 2013-03-14 |
US8546952B2 (en) | 2013-10-01 |
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