TW201347120A - 半導體晶片，具有該半導體晶片之半導體包裝，以及使用該半導體包裝之疊層半導體封裝 - Google Patents

半導體晶片，具有該半導體晶片之半導體包裝，以及使用該半導體包裝之疊層半導體封裝 Download PDF

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Publication number
TW201347120A
TW201347120A TW101132621A TW101132621A TW201347120A TW 201347120 A TW201347120 A TW 201347120A TW 101132621 A TW101132621 A TW 101132621A TW 101132621 A TW101132621 A TW 101132621A TW 201347120 A TW201347120 A TW 201347120A
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Taiwan
Prior art keywords
semiconductor package
electrode
pattern
semiconductor wafer
semiconductor
Prior art date
Application number
TW101132621A
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English (en)
Inventor
Seung-Hee Jo
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Sk Hynix Inc
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Publication of TW201347120A publication Critical patent/TW201347120A/zh

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Abstract

一種半導體封裝，包含一具有一前表面和一後表面之半導體晶片、形成於該半導體晶片以穿過該前表面和後表面且在其前表面設有一第一端以及在其後表面設有一第二端之貫穿電極、及一背側凸塊，該背側凸塊係形成於該貫穿電極之第二端上方，包含一在貫穿電極之第二端一部份上方形成的嵌入式圖案與一在該嵌入式圖案和該貫穿電極第二端之其餘部分上方形成之導電圖案，並且具一凸截面狀。

Description

半導體晶片，具有該半導體晶片之半導體包裝，以及使用該半導體包裝之疊層半導體封裝
本發明係關於一種半導體封裝，特別是一種藉由改變背面凸塊之形狀而提高可靠性之半導體晶片、具有該半導體晶片之半導體封裝、及一使用該半導體封裝之疊層半導體封裝。
本申請案在此聲明以2012年5月03日提出申請之韓國專利申請第10-2012-0047060號主張優先權，該申請之全部內容已合併於本說明中作為參考。
封裝技術的趨勢朝向減少整體尺寸與達到高容量之半導體封裝發展。尤其，儘管高容量可經由落實高度集成半導體設備而實現，要實現高度集成之半導體設備並不容易且具有其本身的限制。因此，高容量係經由裝設至少二片半導體晶片於一封裝而實現。
在一藉由裝設至少二片半導體晶片而實現之疊層半導體封裝中，信號通常是藉由金屬電線而傳輸。然而，對於使用金屬電線而實現之疊層半導體封裝，由於信號傳輸長度較長，因此驅動速度變慢；由於需要額外用於焊線之區域，因此整體尺寸增加，據此造成一些缺失。
在此情況下，在一近來發展之疊層半導體封裝中，使用貫穿電極來電性連接一基板和數片疊層之半 導體晶片。該運用貫穿電極之疊層半導體晶片具有一結構，其中貫穿電極於將要堆疊之半導體晶片上形成，而和該貫穿電極一起形成之半導體晶係藉由貫穿電極之相互連接與一基板物理和電性連接。
為了使貫穿電極相互連接，數個凸塊一般係於所述貫穿電極之兩端形成。當經由接合數個凸塊堆疊該半導體晶片，一非導電膠(NCP)或一非導電膜(NCF)係挿置於各半導體晶片之間。
在此，為了達到高容量堆疊，有必要減少各半導體晶片之間的間隙。為了減少各半導體晶片之間的間隙，應該要減少凸塊的高度。然而，如果減少了凸塊高度，凸塊凹陷會以幾何圖案於底層出現。據此，當接合各半導體晶片時，所述非導電膠(NCP)或非導電膜(NCF)可能會限制於凹陷中，因此各半導體晶片之間的接合強度可能降低，可能導致失敗。尤其，儘管在各凸塊上各貫穿電極之前端(以下稱作「前面凸塊」)不會有凹陷，由於該等前面的凸塊係藉由焊接而形成，因此難以將凹陷由該等凸塊之各貫穿電極的後端(以下稱作「背面凸塊」)移除。
本發明之一實施例係針對一種半導體晶片，可藉由改變背面凸塊的結構而防止凸塊凹陷現象的發生。
且，本發明之一實施例係針對一種具有該半導體 晶片之半導體封裝。
又，本發明之一實施例係針對一種疊層半導體封裝，可藉由改變背面凸塊之結構而防止凸塊凹陷，同時減少數塊凸塊所占據的空間，藉此防止可靠性降低。
在本發明之一實施例，一半導體晶片係包含數個在焊墊上方形成作為連接至一外部電路之連接構件之凸塊，該等凸塊包括：於一部份焊墊上方形成之嵌入式圖案；及一在該嵌入式圖案上方和該焊墊其餘部份形成之導電圖案，該凸塊具有一凸截面狀。
該半導體晶片又包括一絕緣圖案，係於該半導體晶片上方形成，以此方式曝露該等焊盤。
該嵌入式圖案可設置於該焊墊之中間部份上方。
該半導體晶片又包括一設置於該焊墊和該嵌入式圖案以及該焊墊和該導電圖案之間的籽晶金屬。
該嵌入式圖案可由與該籽晶金屬同樣類型的金屬組成。
該導電圖案可包括一電鍍層，其係藉由使用該籽晶金屬嵌入式圖案作為一籽晶而生長。
該半導體晶片又可包括一設置於該焊墊和該導電圖案之間以及在該嵌入式圖案和該導電圖案之間的籽晶金屬。
該嵌入式圖案可由一介電質組成。
該導電圖案可包括一電鍍層，係藉由使用該籽晶金屬作為一籽晶而生長。
該焊墊可包含焊盤或再分配焊墊。
在本發明之另一實施例中，一半導體封裝包括：一具有一前表面和一後表面之半導體晶片；貫穿電極，形成於該半導體晶片而通過該前表面和後表面，並具有一置於該前表面上之第一端和一置於該後表面上之第二端；及背側凸塊，係於該貫穿電極之第二端上方形成，包含一在該貫穿電極第二端之一部份形成之嵌入式圖案和一在該嵌入式圖案與該貫穿電極第二端之其餘部份上方形成之導電圖案，並且具一凸截面狀。
該半導體封裝又可包括一絕緣圖案，係於該半導體晶片之後表面上方形成，以此方式曝露該貫穿電極之第二端。
該半導體封裝又可包括在該貫穿電極之第一端上方形成之前面凸塊。
該半導體封裝並可包括複數個在該貫穿電極之第一端上方形成之前面凸塊。
該嵌入式圖案可設置於該已曝露之貫穿電極第二端的中間部份。
該背側凸塊又可包括一設置於該貫穿電極之第二端和該嵌入式圖案之間以及在該貫穿電極之第二 端和該導電圖案之間的籽晶金屬。
該嵌入式圖案可由與該籽晶金屬同樣類型的金屬所組成。
該導電圖案可包括一電鍍層，係藉由使用該籽晶金屬和該嵌入式圖案作為一籽晶而生長。
該半導體封裝又可包括一設置於該貫穿電極之第二端和該導電圖案之間以及在該嵌入式圖案和該導電圖案之間的籽晶金屬。
該嵌入式圖案可由一介電質組成。
該導電圖案可包括一電鍍層，係使用該籽晶金屬作為一籽晶而生長。
在本發明之另一實施例，一疊層半導體封裝包含：一第一半導體封裝，包括一具有一前表面和一後表面之半導體晶片；數個貫穿電極，係於該半導體晶片形成且通過該前表面和後表面，並且具有一置於該前表面上之第一端和一置於該後表面之第二端；在該貫穿電極之第一端上方形成之前面凸塊；以及背側凸塊，在該貫穿電極之第二端上方形成，包含一在該貫穿電極第二端之一部份上方形成之嵌入式圖案和一在該嵌入式圖案和該貫穿電極第二端之其餘部份上方形成之導電圖案，並且具有一凸截面狀。至少一第二半導體封裝係堆疊於該第一半導體封裝上方並且具有一大致與第一半導體封裝相同之配置方式，該第 二半導體封裝之背側凸塊係與一底層半導體封裝之前面凸塊相接；一第三半導體封裝係堆疊於一位於疊層第二半導體封裝最上面位置之第二半導體封裝上方，並具有與該最上面第二半導體封裝之前面凸塊相接之背側凸塊，並且包含一嵌入式圖案和一呈凸截面狀之導電圖案。
該疊層半導體封裝又包括絕緣圖案，係形成於該半導體晶片各後表面之上方，以此方法曝露該貫穿電極之第二端。
該嵌入式圖案可設置於該已曝露之貫穿電極第二端之中間部份上。
該背側凸塊又可包括一設置於該貫穿電極之第二端和該嵌入式圖案之間以及在該貫穿電極之第二端和該導電圖案之間的籽晶金屬。
該嵌入式圖案可由具有和該籽晶金屬同樣類型之金屬所組成。
該導電圖案可包含一電鍍層，其係藉由使用該籽晶金屬和該嵌入式圖案作為一籽晶而生長。
該疊層半導體封裝又可包括一設置於該貫穿電極之第二端和該導電圖案之間以及在該嵌入式圖案和該導電圖案之間的籽晶金屬。
該嵌入式圖案可由一介電質組成。
該導電圖案可包括一電鍍層，係藉由使用該籽晶 金屬作為一籽晶而生長。
該疊層半導體封裝又可包括設置在該第一半導體封裝之前面凸塊和該第二半導體封裝之背側凸塊之間以及在該第二半導體封裝之前面凸塊和該第三半導體封裝之背側凸塊之間的連接構件。
該疊層半導體封裝又可包括填佈於疊層第一和第二半導體封裝之間以及在疊層第二和第三半導體封裝之間間隔的底部填充構件。
該疊層半導體封裝又可包括一結構體，係支撐該疊層第一和第二半導體封裝並在一表面上具有連接電極，其係藉由該第一半導體封裝之背側凸塊與該第一半導體封裝之貫穿電極電性連接。
該結構體可包括一印刷電路板、一中介層、及一第四半導體封裝其中任一者。
該疊層半導體封裝又可包括；一封膜構件，係在該結構體之一表面形成以覆蓋該疊層第一和第二半導體封裝；及數個外部連接端，係設置於與前述該面相對之該結構體之另一面。
茲將參照附加圖示詳細說明本發明之各實施例。
在此須瞭解，附加圖示不一定依照比例，在某些情況下，比例可能被誇大，以便更清楚地描述本發明的某些特徵。
第1、2圖係繪示根據本發明之一實施例之半導體晶片之剖視圖。
參照第1、2圖，一根據本發明一實施例之半導體晶片100包含一半導體晶片體110、數個焊盤120、及數個凸塊140。且，根據本發明此實施例之半導體晶片100又包括一形成以曝露該焊盤120之絕緣圖案130。
該半導體晶片體110具有，例如，一矩形六面體狀且包含一活性表面111。該半導體晶片體110可由一其中之電路單元所構成。
例如，所述焊盤120可為接合焊盤。在此情況下，該焊盤120係設置於該半導體晶片體110之活性表面111上，並且與形成於該半導體晶片體110之電路單元電性連接。
焊盤120也可以為數個再分配焊墊。當作為再分配焊墊，雖然未顯示於圖示中，該焊盤120可以是部份的再分配線，而且不僅可設置於該半導體晶片體110之活性表面111，而且可設置於與該活性表面111相對之該半導體晶片體110之另一表面。
凸塊140係包含在部份該等焊盤120上形成之嵌入式圖案142。該等凸塊140又可包含於該等嵌入式圖案142和該焊盤120之其餘部份上方形成之導電圖案146，並且具有一凸截面狀。
在一實施例，如第1圖所示，該等凸塊140又包 括一籽晶金屬144，係設置於該焊盤120和該嵌入式圖案142之間，及設置於該焊盤120和該導電圖案146之間。該等嵌入式圖案142係由與該籽晶金屬144大致相同和(或)完全相同的金屬所組成。該導電圖案146係由一電鍍層組成，該電鍍層係經由使用該籽晶金屬144和該嵌入式圖案142作為一籽晶(例如：一銅電鍍層)而生長。
在第2圖所示之另一實施例中，數個凸塊140又包括一籽晶金屬144，係設置於該焊墊120和該導電圖案146之間，及設置於該嵌入式圖案142和該導電圖案146之間。該嵌入式圖案142係由一介電質組成，該導電圖案146係由一電鍍層組成，該電鍍層係經由使用該籽晶金屬144作為一籽晶(例如：一銅電鍍層)而生長。
在依據上述實施例之半導體晶片中，由於存在該嵌入式圖案，由一電鍍層構成之導電圖案可具有一凸截面狀。因此，當觀察整體時，包含該嵌入式圖案和該導電圖案之數個凸塊可具有一凸截面狀。
據此，由於根據此實施例之半導體晶片包含數個具有凸截面狀之凸塊，當該半導體晶片經由該數個凸塊而裝附於一外部電路上，數個凸塊上不會發生凹陷，因此可提升在該外部電路安裝該半導體晶片之可靠性。
第3圖係一根據本發明另一實施例顯示一半導 體封裝之橫截面圖。
參照第3圖，根據本發明之另一實施例之一半導體封裝300包含一半導體晶片310、貫穿電極320、及背面凸塊340。
該半導體晶片310具有一前表面311和一與該前表面311相對之後表面312。雖未示於圖示中，該半導體晶片310包含數個設置於其前表面311之接合焊盤和一於其中形成之電路單元。該數個接合焊盤可配置於該半導體晶片310之前表面311中間部份之一條線或兩條線上。在此實施例之另一變異，該數個接合焊盤可配置於該前表面311至少一邊緣和與所述邊緣相對之該前表面311之另一邊的一條線或兩條線上，亦或，該數個接合焊盤可沿著該前表面311邊緣之一條或二條線配置。該電路單元係形成於鄰接該前表面311之半導體晶片310的內側部份，並且可包含，例如，一用以儲存資料之資料儲存區和一用以處理資料之資料處理區。
該貫穿電極320形成時係通過該半導體晶片310之前表面311和後表面312。該貫穿電極320具有設置於該半導體晶片310之前表面311的第一端321和設置於該半導體晶片310之後表面312之第二端322。雖然未顯示於圖示中，該貫穿電極320係以一對一對應的方式與設置於半導體晶片310之前表面311之接合焊盤電性連接。對此，該貫穿電極320形 成時係通過相對應之接合焊盤，因此其第一端321可直接與該相對應之接合焊盤電性連接。在此實施例之另一變異中，該貫穿電極320可在形成時通過鄰近對應的接合焊盤之部份半導體晶片，該貫穿電極320之第一端321可經由再分配線之類與相對應之接合焊盤電性連接。
根據本實施例之半導體封裝300又包括一絕緣圖案330，該絕緣圖案330係形成於該半導體晶片310之後表面312，以此方式曝露該貫穿電極320之第二端322。該絕緣圖案330可以形成而如圖所示般部份曝露該貫穿電極320之第二端322。在此實施例之另一變異中，該絕緣圖案330可以形成而完全曝露該貫穿電極320之第二端322。
該背面凸塊340，係形成於該貫穿電極320第二端322之已曝露部份以及鄰近該貫穿電極320第二端322之已曝露部份之部份絕緣圖案330。詳言之，該背面凸塊340係包含形成於該貫穿電極320第二端322之部份已曝露部份之嵌入式圖案342，及形成於該嵌入式圖案342、該貫穿電極320第二端322之其餘已曝露部份、及鄰近該貫穿電極320第二端322之已曝露部份之部份的絕緣圖案330之導電圖案346。
在此實施例，該嵌入式圖案342係於該貫穿電極320之第二端322之一部份已曝露部份形成以防止凸塊凹陷的發生。該嵌入式圖案342可在形成時設置於 該貫穿電極320之第二端322之已曝露部份之中間。舉例而言，該嵌入式圖案342係由一金屬所構成。茲將在後面清楚描述，該等嵌入式圖案342係由與用以形成該導電圖案346之一籽晶金屬144大致相同和(或)完全相同的金屬所組成。由所述金屬構成之嵌入式圖案342可藉由，例如，類似焊線之熱壓縮而形成。
在第3圖所示之一實施例中，該半導體封裝300之背面凸塊340又包括一介於該貫穿電極320之第二端322和該嵌入式圖案342之間及介於該貫穿電極320之第二端322和該導電圖案346之間的籽晶金屬344。該嵌入式圖案342係由與該籽晶金屬344大致相同和(或)完全相同之金屬所組成，該導電圖案346係由一電鍍層構成，而該電鍍層係藉由使用該籽晶金屬344和該嵌入式圖案342作為一籽晶(例如：一銅電鍍層)而生長。
在另一實施例，雖然未顯示於圖示中，該半導體封裝300之背面凸塊340又包括一介於該貫穿電極320之第二端和該導電圖案346以及介於該嵌入式圖案342和該導電圖案346之間之籽晶金屬344。該嵌入式圖案342係由一介電質所組成，而該導電圖案346係由一電鍍層構成，該電鍍層係藉由使用該籽晶金屬344作為一籽晶(例如：一銅電鍍層)而生長。
另外，根據此實施例之半導體封裝300又包括一額外的絕緣圖案350，該絕緣圖案350係在該半導體 晶片310之前表面311形成，以此方式曝露該貫穿電極320之第一端321；及數個前面凸塊360，係在該被曝露之貫穿電極320之第一端321的一部份形成。
在上述根據此實施例之半導體封裝中，由於存在的嵌入式圖案，該背面凸塊具有一凸截面狀。因此，當該半導體封裝藉由該數個凸塊裝載於一外部電路，由於數個凸塊中不會出現凹陷，因此依據此實施例之半導體封裝具有改善的安裝可靠性。
第4、5圖係根據本發明之另一實施例之疊層半導體封裝的橫截面圖。
參照第4、5圖，根據本發明之另一實施例之一疊層半導體封裝400包含一第一半導體封裝410和至少一第二半導體封裝420。且，根據本發明另一實施例之疊層半導體封裝400又包括一底部填充構件460，例如非導電膠(NCP)或非導電膜(NCF)，係填佈於該疊層半導體封裝410、420之間的間隙中。
第一半導體封裝410包含一半導體晶片412，係具有一前表面和與一該前表面相對之後表面；貫穿電極414，在該半導體晶片412形成以通過該前表面和後表面，並具有設置於該前表面之第一端和設置於該後表面之第二端；數個前面凸塊416，係形成於該貫穿電極414之第一端；及數個背面凸塊418，係形成於該貫穿電極414之第二端。該數個凸塊416、418可被配置為數個連接構件。且，該第一半導體封裝 410又包括一絕緣圖案419，係形成於該後表面，以此方式曝露該貫穿電極414之第二端。
該背面凸塊418係包含介於該貫穿電極414第二端之一部份的嵌入式圖案418a與介於該嵌入式圖案418a和設置於該貫穿電極414第二端之其餘部份的導電圖案418c。該導電圖案418c可具有一凸截面狀。該嵌入式圖案418a可設置於該貫穿電極414第二端之曝露部份的中間部份。
在一實施例中，該背面凸塊418又包括一介於貫穿電極414之第二端和該嵌入式圖案418a以及介於該貫穿電極414之第二端和該導電圖案418c之間的籽晶金屬418b。該嵌入式圖案418a可由與該籽晶金屬418b大致相同和(或)完全相同之金屬所組成，該導電圖案418c係由一經由使用該籽晶金屬418b和該嵌入式圖案418a作為一籽晶而生長之電鍍層所構成。
在另一實施例，雖然未顯示於圖示中，該數個凸塊418又包括一介於該貫穿電極414之第二端和該導電圖案418c之間以及介於該嵌入式圖案418a和該導電圖案418c之間的籽晶金屬418b。該嵌入式圖案418a係由一介電質組成，該導電圖案418c係由一經由使用該籽晶金屬418b作為一籽晶而生長之電鍍層所構成。
至少一第二半導體封裝420係堆疊於該第一半 導體封裝410上。在此實施例，係有一第二半導體封裝420被堆疊。該第二半導體封裝420具有一與第一半導體封裝410大致相同和(或)完全相同的配置方式。尤其，該第二半導體封裝420之背面凸塊418係經由連接構件450，例如焊料，與在該第一半導體封裝410下面之數個前面凸塊416電性連接。
雖然未顯示於圖示，至少有兩個第二半導體封裝，例如半導體封裝420，可以被堆疊。當置少有兩個第二半導體封裝420堆疊時，該連接構件450可能被挿置於其中，並且使較高位置之半導體封裝的背面凸塊418與較低位置之半導體封裝的數個前面凸塊416電性連接。
根據此實施例之疊層半導體封裝400又包括一第三半導體封裝430，其係堆疊於該第二半導體封裝420上或堆疊於在第二半導體封裝410、420之中位於最上面的第二半導體封裝420上。除了數個前面凸塊並非形成於該貫穿電極414之第一端外，該第三半導體封裝430可具有與該第一半導體封裝410和第二半導體封裝420大致相同和(或)完全相同之配置方式。亦即，該第三半導體封裝430之背面凸塊418係藉由該連接構件450與在該第二半導體封裝420下面之數個前面凸塊電性連接。
該第三半導體封裝430可包含一與第一半導體封裝410和第二半導體封裝420大致相通和(或)完全 相同類型之半導體晶片，亦或第三半導體封裝430可能包含一與第一半導體封裝410和第二半導體封裝420不同類型的半導體晶片，例如一驅動晶片。
根據此實施例之疊層半導體封裝400又包括一結構體，其係設置於該第一半導體封裝410之下面。
該結構體可為一第四半導體封裝440，具有作為連接電極之貫穿電極444和數個前面凸塊446，如第4圖所示。該第四半導體封裝440包含一半導體晶片442，係具有一前表面和一與該前表面相對之後表面；及貫穿電極444，係形成時通過該前表面和後表面，並且具有設置於該前表面之第一端和設置於該後表面之第二端。該第四半導體封裝440亦可包含數個於該貫穿電極444第一端形成之前面凸塊446以及再分配線448，係於半導體晶片442之後表面形成，使得該再分配線448之一端與該貫穿電極444之第二端相接。該第四半導體封裝440可包含一與該第一半導體封裝410、第二半導體封裝420、及第三半導體封裝430大致相同和(或)完全相同或不同類型之記憶體晶片。
該結構體可為一具有連接電極(如指狀焊條)之印刷電路板470，如第5圖所示。該印刷電路板470包含設置於其上表面作為連接電極之指狀焊條472與設置於其下表面之錫球盤474。
雖然未顯示於圖示中，該結構體可為一具有連接 電極之中介層。
根據此實施例之疊層半導體封裝400又包括外部連接端490，如錫球，其係附著於該第四半導體封裝440之再分配線448上，如第4圖所示。
根據此實施例之疊層半導體封裝400又可包括一封膜構件480，其係於該印刷電路板470之一上表面形成，以覆蓋該疊層之第一半導體封裝410、第二半導體封裝420、及第三半導體封裝430。該封膜構件480可以於該外部連接端490之上方形成，例如附著於設於該印刷電路板470下表面之錫球盤474之錫球，如第5圖所示。
根據此實施例之疊層半導體封裝中，由於該背面凸塊由於存在之嵌入式圖案而具一凸截面狀，不會發生凸塊凹陷現象。因此，當堆疊第一、第二、及第三半導體封裝或當堆疊各第二半導體封裝時，一底部填充構件，如一非導電膠(NCP)或非導電膜(NCF)，被限制於該背面凸塊所導致的缺失不會出現。
據此，在根據此實施例之疊層半導體封裝，由於各個半導體封裝之間的接合強度沒有降低，不導致失敗，因此會顯著改善該疊層半導體封裝之特性與可靠性。
第6圖係顯示一依本發明包含該半導體封裝之電子設備之透視圖。
參照第6圖，根據本發明一實施例之半導體封裝 可由一電子設備1000(例如：一行動電話)實行。由於根據本發明之實施例之半導體封裝能實現良好的安裝可靠性，係提出改善該電子設備1000特性之優點。該電子設備1000並不限於第6圖所示之行動電話，也可以包含各種電子設備，如行動電子設備、膝上型電腦、筆記型電腦、便攜式多媒體播放器(PMP)、MP3播放器、攝像機，網路平板電腦、無線手機、導航器、個人數字助理(PDA)等等。
第7圖係顯示依本發明之一包含該半導體封裝之電子系統範例之方塊圖。
參照第7圖，一電子系統700可包含一控制器710、一輸入/輸出單元720、及一記憶體730。該控制器710、輸入/輸出單元720、及記憶體730可藉由一匯流排750而相互耦合。該匯流排750可為一讓資料移動之路徑。
舉例而言，該控制器710可包含一微控制器、至少一數位信號處理器、至少一微控制器、及能夠執行與前述元件相同功能之邏輯裝置之其中任一者。該控制器710與該記憶體730可包含一根據本發明一實施例之半導體封裝。
輸入/輸出單元720可包含選自一小鍵盤、一鍵盤、一顯示器等當中之其中一者。
記憶體730係一用以儲存資料之元件。該記憶體730可儲存資料和(或)由該控制器710執行之指令之 類。該記憶體730可包含一揮發記憶體裝置和(或)一非揮記憶體裝置。又，該記憶體730可由一快閃記憶體組成。例如，本發明技術所應用之快閃記憶體可被裝設於一資訊處理系統，如行動設備或桌上型電腦。快閃記憶體可由一固態硬碟(SSD)組成。在此情況下，該電子系統700可以將大量的資料穩定地儲存於一快閃記憶體系統。
電子系統700可能又包括一配置以傳送資料到一通信網路和由該通信網路接收資料之介面740。該介面740可為有線或無線形式。例如，該介面740可包含一天線或一有線或無線收發器。
再者，雖然未顯示於圖示，那些熟知此技術領域的人將輕易理解到該電子系統700可以另外提供一應用晶片集、一相機圖像處理器(CIP)、及輸入/輸出裝置等。
雖然本發明之各例示實施例僅用以作為圖示說明，熟習該項技術者應知悉各種修改、增加、及替代而沒有偏離以下申請專利範圍所揭示之本發明的範圍與精神皆是有可能。
100‧‧‧半導體晶片
110‧‧‧半導體晶片體
111‧‧‧活性表面
120‧‧‧焊盤
130‧‧‧絕緣圖案
140‧‧‧凸塊
142‧‧‧嵌入式圖案
144‧‧‧籽晶金屬
146‧‧‧導電圖案
300‧‧‧半導體封裝
310‧‧‧半導體晶片
311‧‧‧前表面
312‧‧‧後表面
320‧‧‧貫穿電極
321‧‧‧第一端
322‧‧‧第二端
330‧‧‧絕緣圖案
340‧‧‧背面凸塊
342‧‧‧嵌入式圖案
344‧‧‧籽晶金屬
346‧‧‧導電圖案
350‧‧‧絕緣圖案
360‧‧‧前面凸塊
400‧‧‧疊層半導體封裝
410‧‧‧第一半導體封裝
412‧‧‧半導體晶片
414‧‧‧貫穿電極
416‧‧‧前面凸塊
418‧‧‧背面凸塊
418a‧‧‧嵌入式圖案
418b‧‧‧籽晶金屬
418c‧‧‧導電圖案
419‧‧‧絕緣圖案
420‧‧‧第二半導體封裝
430‧‧‧第三半導體封裝
440‧‧‧第四半導體封裝
442‧‧‧半導體晶片
444‧‧‧貫穿電極
446‧‧‧前面凸塊
448‧‧‧再分配線
450‧‧‧連接構件
460‧‧‧底部填充構件
470‧‧‧印刷電路板
472‧‧‧指狀焊條
474‧‧‧錫球盤
480‧‧‧封膜構件
490‧‧‧外部連接端
700‧‧‧電子系統
710‧‧‧控制器
720‧‧‧輸入/輸出單元
730‧‧‧記憶體
740‧‧‧介面
750‧‧‧匯流排
1000‧‧‧電子設備
第1、2圖係顯示根據本發明一實施例之半導體晶片的橫截面圖。
第3圖係顯示一根據本發明另一實施例之半導體晶片的橫截面圖。
第4、5圖係顯示根據本發明另一實施例之疊層半導體封裝的橫截面圖。
第6圖係一根據本發明之一包含該半導體封裝之電子設備的透視圖。
第7圖係一根據本發明顯示一包含該半導體封裝之電子系統範例的方塊圖。
400‧‧‧疊層半導體封裝
410‧‧‧第一半導體封裝
412‧‧‧半導體晶片
414‧‧‧貫穿電極
416‧‧‧前面凸塊
418‧‧‧背面凸塊
418a‧‧‧嵌入式圖案
418b‧‧‧籽晶金屬
418c‧‧‧導電圖案
419‧‧‧絕緣圖案
420‧‧‧第二半導體封裝
430‧‧‧三半導體封裝
440‧‧‧第四半導體封裝
442‧‧‧半導體晶
444‧‧‧貫穿電極
446‧‧‧前面凸塊
448‧‧‧再分配線
450‧‧‧連接構件
460‧‧‧底部填充構件
490‧‧‧外部連接端

Claims (20)

  1. 一種半導體晶片，包括數個焊墊上方形成作為連接一外部電路之連接構件之凸塊，該等凸塊包括：一嵌入式圖案，形成在一部份焊墊之上方；及一導電圖案，形成在該嵌入式圖案和該焊墊之其餘部份上方，且具有一凸截面狀。
  2. 如申請專利範圍第1項之半導體晶片，其尚包含：一絕緣圖案，形成在該半導體晶片上方，以此方式曝露該半導體晶片。
  3. 如申請專利範圍第1項之半導體晶片，其中該嵌入式圖案係設置於該焊墊一中間部份上方。
  4. 如申請專利範圍第1項之半導體晶片，其尚包含：一籽晶金屬，係設置在該焊墊和該嵌入式圖案之間以及在該焊墊和該導電圖案之間。
  5. 如申請專利範圍第4項之半導體晶片，其中該嵌入式圖案係由和籽晶金屬同樣類型的金屬所組成。
  6. 如申請專利範圍第4項之半導體晶片，其中該導電圖案包括一電鍍層，係藉由使用籽晶金屬和該嵌入式圖案作為一籽晶而生長。
  7. 如申請專利範圍第1項之半導體晶片，其尚包含：一籽晶金屬，係設置在該焊墊和該導電圖案之間以及在該嵌入式圖案和該導電圖案之間。
  8. 如申請專利範圍第7項之半導體晶片，其中該嵌入式圖案係由一介電質組成。
  9. 如申請專利範圍第7項之半導體晶片，其中該導電圖案包括一電鍍層，其係藉由使用該籽晶金屬作為一籽晶而生長。
  10. 如申請專利範圍第1項之半導體晶片，其中該焊墊包括焊盤或再分配焊墊。
  11. 一種半導體包裝，包含：一半導體晶片，具有一前表面及一後表面；貫穿電極，係形成於該半導體晶片且通過該前表面和後表面，並具有一置於前表面上之第一端和一置於後表面上之第二端；以及背側凸塊，係形成於該貫穿電極之第二端上方，包含一在該貫穿電極之第二端一部份上方形成之嵌入式圖案與一在該嵌入式圖案和該貫穿電極之第二端其餘部份上方形成之導電圖案，並且具一凸截面狀。
  12. 如申請專利範圍第11項之半導體包裝，其尚包含：一絕緣圖案，係於該半導體晶片之後表面上方形成，以此方式曝露該貫穿電極之第二端。
  13. 如申請專利範圍第11項之半導體包裝，其尚包含：在該貫穿電極第一端上方形成之前面凸塊。
  14. 如申請專利範圍第11項之半導體包裝，其中該嵌入式圖案係設置於該貫穿電極第二端之中間部份上方。
  15. 如申請專利範圍第11項之半導體包裝，其背側凸塊尚包含：一籽晶金屬，係設置在該貫穿電極之第二端和該嵌入式圖案之間以及在該貫穿電極之第二端和該導電圖案之間。
  16. 如申請專利範圍第15項之半導體包裝，其中該嵌入式圖案係由與該籽晶金屬同樣類型之金屬所組成。
  17. 如申請專利範圍第11項之半導體包裝，其中該導電圖案包括一電鍍層，其係藉由使用該籽晶金屬和嵌入式圖案作為一籽晶而生長。
  18. 如申請專利範圍第11項之半導體包裝，其尚包含：一籽晶金屬，係設置在該貫穿電極之第二端和該導電圖案之間以及在該嵌入式圖案和該導電圖案之間。
  19. 如申請專利範圍第18項之半導體包裝，其中該嵌入式圖案係由一介電質組成。
  20. 如申請專利範圍第18項之半導體包裝，其中該導電圖案包括一電鍍層，係藉由使用籽晶金屬作為一籽晶而生長。
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