CN103383928A - 半导体芯片及半导体封装体 - Google Patents

半导体芯片及半导体封装体 Download PDF

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Publication number
CN103383928A
CN103383928A CN2013100651826A CN201310065182A CN103383928A CN 103383928 A CN103383928 A CN 103383928A CN 2013100651826 A CN2013100651826 A CN 2013100651826A CN 201310065182 A CN201310065182 A CN 201310065182A CN 103383928 A CN103383928 A CN 103383928A
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China
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pattern
package body
semiconductor package
semiconductor chip
penetrating electrode
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CN2013100651826A
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赵胜熙
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SK Hynix Inc
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Hynix Semiconductor Inc
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Publication of CN103383928A publication Critical patent/CN103383928A/zh
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Abstract

本发明公开了半导体芯片及半导体封装体。该半导体封装体包括：具有前表面和背表面的半导体芯片；贯穿电极，在半导体芯片中形成为穿过前表面和背表面，且具有设置在前表面上的第一端以及设置在背表面上的第二端；以及背侧凸块，形成于贯穿电极的第二端上方，包括形成在贯穿电极的第二端的一部分上方的埋入图案和形成在埋入图案和贯穿电极的第二端的其余部分上方的导电图案，并且具有凸起的截面形状。

Description

半导体芯片及半导体封装体
技术领域
本发明涉及半导体封装体，更具体涉及通过改变背侧凸块的形状而提高可靠性的半导体芯片、具有该半导体芯片的半导体封装体、以及使用该半导体封装体的堆叠半导体封装体。
背景技术
封装技术的趋势朝向减少整体尺寸与实现高容量的半导体封装体发展。尤其，尽管高容量可通过实现高度集成的半导体装置而实现，但是要实现高度集成的半导体装置并不容易且具有其本身的限制。因此，通过在一个封装体中安装至少两个半导体芯片而实现高容量。
在通过安装至少二个半导体芯片而实现的堆叠半导体封装体中，通常通过金属布线将信号传送至各个堆叠的半导体芯片。然而，在使用金属布线而实现的堆叠半导体封装体的情况下，引起的缺点在于，驱动速度由于信号传输长度长而变慢；整体尺寸由于需要额外的区域用于引线接合而增加。
在此情况下，在近来发展的堆叠半导体封装体中，贯穿电极用于电性连接基板和堆叠的半导体芯片。采用贯穿电极的堆叠半导体封装体具有这样的结构，其中贯穿电极形成在各个要堆叠的半导体芯片中，形成有贯穿电极的半导体芯片通过相互连接贯穿电极而彼此物理和电性连接并且与基板物理和电性连接。
为了使贯穿电极相互连接，凸块通常形成于贯穿电极的两端。当经由接合凸块而堆叠半导体芯片时，非导电胶（NCP）或非导电膜（NCF）插设于半导体芯片之间。
这里，为了实现高容量堆叠，需要减少半导体芯片之间的间隙。为了减少半导体芯片之间的间隙，应减少凸块的高度。然而，如果减少了凸块高度，由于底层的几何形状会出现凸块凹陷，由于这样的事实，当使半导体芯片彼此接合时，NCP或NCF易于陷入凹陷中，由此半导体芯片之间的接合强度可能劣化从而可能导致失效。具体地，尽管在贯穿电极前端上的凸块（以下称作“前侧凸块”）上典型地不会有凹陷，由于前侧凸块通过焊接形成，但却难以从贯穿电极的后端上的凸块（以下称作“背侧凸块”）移除凹陷。
发明内容
本发明的实施例涉及半导体芯片，可通过改变背侧凸块的结构而防止凸块凹陷现象的发生。
而且，本发明的实施例涉及具有半导体芯片的半导体封装体。
此外，本发明的实施例涉及堆叠半导体封装体，其可通过改变背侧凸块的结构而防止凸块凹陷，同时减少凸块所占据的空间，由此防止可靠性劣化。
在本发明的一个实施例中，半导体芯片包括形成在焊垫上方作为连接至外部电路的连接构件的凸块，凸块包括：埋入图案，形成于焊垫的一部分上方；以及导电图案，形成在埋入图案和焊垫的其余部分上方且具有凸起的截面形状。
半导体芯片还包括绝缘图案，以暴露焊垫的方式形成于半导体芯片上方。
埋入图案可设置于焊垫的中间部分上方。
半导体芯片还可包括设置于焊垫和埋入图案以及焊垫和导电图案之间的籽晶金属。
埋入图案可由与籽晶金属相同类型的金属形成。
导电图案可包括通过使用籽晶金属和埋入图案作为籽晶而生长的电镀层。
半导体芯片还可包括设置于焊垫和导电图案之间以及埋入图案和导电图案之间的籽晶金属。
埋入图案可由电介质物质形成。
导电图案可包括通过使用籽晶金属作为籽晶而生长的电镀层。
焊垫可包括接合焊垫或重分配焊垫。
在本发明的另一实施例中，半导体封装体包括：具有前表面和背表面的半导体芯片；贯穿电极，在半导体芯片中形成为穿过前表面和背表面，并具有设置于前表面上的第一端和设置于背表面上的第二端；以及背侧凸块，形成于贯穿电极的第二端上方，包括形成在贯穿电极的第二端的一部分上方的埋入图案和形成在埋入图案和贯穿电极的第二端的其余部分上方的导电图案，并且具有凸起的截面形状。
半导体封装体还可包括绝缘图案，以暴露贯穿电极的第二端的方式形成于半导体芯片的背表面上方。
半导体封装体还可包括形成在贯穿电极的第一端上方的前侧凸块。
半导体封装体还可包括形成在贯穿电极的第一端上方的前侧凸块。
埋入图案可设置于贯穿电极的暴露的第二端的中间部分上方。
背侧凸块还可包括设置于贯穿电极的第二端和埋入图案之间以及贯穿电极的第二端和导电图案之间的籽晶金属。
埋入图案可由与籽晶金属相同类型的金属形成。
导电图案可包括通过使用籽晶金属和埋入图案作为籽晶而生长的电镀层。
半导体封装体还可包括设置于贯穿电极的第二端和导电图案之间以及埋入图案和导电图案之间的籽晶金属。
埋入图案可由电介质物质形成。
导电图案可包括使用籽晶金属作为籽晶而生长的电镀层。
在本发明的又一实施例中，堆叠半导体封装体包括：第一半导体封装体，包括具有前表面和背表面的半导体芯片；贯穿电极，在半导体芯片中形成为穿过前表面和背表面，并且具有设置于前表面上的第一端和设置于背表面上的第二端；前侧凸块，形成在贯穿电极的第一端上方；以及背侧凸块，形成在贯穿电极的第二端上方，包括形成在贯穿电极的第二端的一部分上方的埋入图案和形成在埋入图案和贯穿电极的第二端的其余部分上方的导电图案，并且具有凸起的截面形状；至少一第二半导体封装体，堆叠于第一半导体封装体上方并且具有如第一半导体封装体的实质构造，第二半导体封装体的背侧凸块与下面的半导体封装体的前侧凸块相连接；以及第三半导体封装体，堆叠于堆叠的第二半导体封装体当中的位置最上的第二半导体封装体上方，并且具有与最上的第二半导体封装体的前侧凸块相连接的背侧凸块，并且包括埋入图案和具有凸起的截面形状的导电图案。
堆叠半导体封装体还包括绝缘图案，以暴露贯穿电极的第二端的方式形成于半导体芯片的各个背表面上方。
埋入图案可设置于贯穿电极的暴露的第二端的中间部分上方。
背侧凸块还可包括设置于贯穿电极的第二端和埋入图案之间以及贯穿电极的第二端和导电图案之间的籽晶金属。
埋入图案可由具有与籽晶金属相同类型的金属形成。
导电图案可包括通过使用籽晶金属和埋入图案作为籽晶而生长的电镀层。
堆叠半导体封装体还可包括设置于贯穿电极的第二端和导电图案之间以及埋入图案和导电图案之间的籽晶金属。
埋入图案可由电介质物质形成。
导电图案可包括通过使用籽晶金属作为籽晶而生长的电镀层。
堆叠半导体封装体还可包括设置在第一半导体封装体的前侧凸块和第二半导体封装体的背侧凸块之间以及第二半导体封装体的前侧凸块和第三半导体封装体的背侧凸块之间的连接构件。
堆叠半导体封装体还可包括填充于堆叠的第一和第二半导体封装体之间以及堆叠的第二和第三半导体封装体之间的空间中的底填构件。
堆叠半导体封装体还可包括结构体，支撑堆叠的第一和第二半导体封装体并在其一个表面上具有连接电极，连接电极通过第一半导体封装体的背侧凸块与第一半导体封装体的贯穿电极电性连接。
结构体可包括印刷电路板、插入体、及第四半导体封装体中的任一者。
堆叠半导体封装体还可包括；模制构件，形成在结构体的一个表面上以覆盖堆叠的第一和第二半导体封装体；以及外部连接端子，设置于与结构体的与该一个表面相反的另一表面上。
附图说明
图1和2是示出根据本发明实施例的半导体芯片的截面图。
图3是示出根据本发明另一实施例的半导体芯片的截面图。
图4和5是示出根据本发明另一实施例的堆叠半导体封装体的截面图。
图6是示出包括根据本发明的半导体封装体的电子设备的立体图。
图7是示出包括根据本发明的半导体封装体的电子系统的示例的方框图。
具体实施方式
以下，将参照附图详细描述本发明的具体实施例。
在此应理解附图不必依照比例，在某些情况下，比例可能被夸大，以便更清楚地描述本发明的某些特征。
图1和2是示出根据本发明的实施例的半导体芯片的截面图。
参照图1和2，根据本发明实施例的半导体芯片100包括半导体芯片本体110、焊垫120及凸块140。并且，根据本发明实施例的半导体芯片100还包括形成为暴露焊垫120的绝缘图案130。
半导体芯片本体110例如具有矩形六面体形状且包括有源表面111。半导体芯片本体110其中可形成为具有电路单元。
例如，焊垫120可为接合焊垫。在此情况下，焊垫120设置于半导体芯片本体110的有源表面111上，并且与形成于半导体芯片本体110中的电路单元电性连接。
焊垫120也可以为重分配焊垫。当作为重分配焊垫，虽然未示出，但焊垫120可以是部分的重分配线，而且不仅可设置于半导体芯片本体110的有源表面111上，而且可设置于半导体芯片本体110的与有源表面111相反的另一表面上。
凸块140包括埋置图案142，埋置图案142形成在焊垫120的一部分上。凸块140还可包括导电图案146，其形成于埋入图案142和焊垫120的其余部分上并且具有凸起的截面形状。
在一个实施例，如图1所示，凸块140还包括插设于焊垫120和埋入图案142之间以及插设于焊垫120和导电图案146之间的籽晶金属144。埋入图案142由与籽晶金属144实质类似和/或相同的金属形成。导电图案146由通过使用籽晶金属144和埋入图案142作为籽晶而生长的电镀层（例如。铜电镀层）构成。
在另一实施例中，如图2所示，凸块140还包括插设于焊垫120和导电图案146之间以及埋入图案142和导电图案146之间的籽晶金属144。埋入图案142由电介质物质形成，而导电图案146由通过使用籽晶金属144作为籽晶而生长的电镀层（例如，铜电镀层）构成。
在依据上述实施例的半导体芯片中，由于存在埋入图案，由电镀层构成的导电图案可具有凸起的截面形状。因此，当观察它们整体时，包括埋入图案和导电图案的凸块可具有凸起的截面形状。
结果，由于根据实施例的半导体芯片包括具有凸起的截面形状的凸块，当半导体芯片通过这样的凸块而安装于外部电路时，凸块上不会出现凹陷，因此可提升半导体芯片对外部电路的安装可靠性。
图3是示出根据本发明另一实施例的半导体封装体的截面图。
参照图3，根据本发明的另一实施例的半导体封装体300包括半导体芯片310、贯穿电极320、及背侧凸块340。
半导体芯片310具有前表面311和与前表面311相反的背表面312。虽未示出，但是半导体芯片310包括多个设置于其前表面311上的接合焊垫和形成于其中的电路单元。多个接合焊垫可在半导体芯片310的前表面311的中间部分上布置成一条线或两条线。在此实施例的另一变型中，多个接合焊垫可在前表面311的至少一个边缘以及与该边缘相反的前表面311的另一边缘上布置成一条线或两条线，或者多个接合焊垫可沿着前表面311的边缘布置成一条线或两条线。电路单元形成于邻近前表面311的半导体芯片310的内侧部分中，并且例如可包括用以储存数据的数据储存部分和用以处理数据的数据处理部分。
贯穿电极320形成为穿过半导体芯片310的前表面311和背表面312。贯穿电极320具有设置于半导体芯片310的前表面311上的第一端321和设置于半导体芯片310的背表面312上的第二端322。虽然未示出，但贯穿电极320以一一对应的方式与设置于半导体芯片310的前表面311的接合焊垫电性连接。为此，贯穿电极320形成为穿过对应的接合焊垫，使得其第一端321可直接与对应的接合焊垫电性连接。在此实施例的另一变型中，贯穿电极320可形成为穿过半导体芯片的邻近对应的接合焊垫的部分，而贯穿电极320的第一端321可经由重分配线等与对应的接合焊垫电性连接。
根据本实施例的半导体封装体300还包括绝缘图案330，绝缘图案330以暴露贯穿电极320的第二端322的方式形成于半导体芯片310的背表面312上。绝缘图案330可以如图中所示以部分暴露贯穿电极320的第二端322的方式形成。在此实施例的另一变型中，绝缘图案330可以完全暴露贯穿电极320的第二端322的方式形成。
背侧凸块340形成于贯穿电极320的第二端322的暴露部分上以及绝缘图案330的邻近贯穿电极320的第二端322的暴露部分的部分上。详言之，背侧凸块340包括埋入图案342和导电图案346，埋入图案342形成于贯穿电极320的第二端322的部分的暴露部分上，导电图案346形成于埋入图案342、贯穿电极320的第二端322的其余的暴露部分、以及绝缘图案330的邻近贯穿电极320的第二端322的暴露部分的部分上。
在此实施例中，埋入图案342形成在贯穿电极320的第二端322的暴露部分的一部分上以防止凸块凹陷的发生。埋入图案342可形成为设置于贯穿电极320的第二端322的暴露部分的中心。例如，埋入图案342由金属形成。如将在后面清楚描述的，埋入图案342由与形成导电图案346的籽晶金属实质类似和/或相同的金属形成。由这样的金属制成的埋入图案342例如可通过类似引线接合的热压缩而形成。
在一个实施例中，如图3所示，半导体封装体300的背侧凸块340还包括插设于贯穿电极320的第二端322和埋入图案342之间以及贯穿电极320的第二端322和导电图案346之间的籽晶金属344。埋入图案342由与籽晶金属344实质类似和/或相同的金属形成，导电图案346由使用籽晶金属344和埋入图案342作为籽晶而生长的电镀层（例如，铜电镀层）构成。
在另一实施例，虽然未示出，半导体封装体300的背侧凸块340还包括插设于贯穿电极320的第二端322和导电图案346之间以及埋入图案342和导电图案346之间的籽晶金属344。埋入图案342由电介质物质形成，而导电图案346由通过使用籽晶金属344作为籽晶而生长的电镀层（例如，铜电镀层）构成。
另外，根据本实施例的半导体封装体300还包括附加的绝缘图案350和前侧凸块360，绝缘图案350以暴露贯穿电极320的第一端321的方式形成在半导体芯片310的前表面311上，前侧凸块360形成在贯穿电极320的暴露的第一端321的一部分上。
在上述根据本实施例的半导体封装体中，由于存在埋入图案，因此背侧凸块具有凸起的截面形状。因此，当半导体封装体通过这样的凸块的方式安装于外部电路时，由于凸块中不会出现凹陷，因此依据本实施例的半导体封装体具有改善的安装可靠性。
图4和5是示出根据本发明的另一实施例的堆叠半导体封装体的截面图。
参照图4和5，根据本发明的另一实施例的堆叠半导体封装体400包括第一半导体封装体410和至少一第二半导体封装体420。并且，根据本发明另一实施例的堆叠半导体封装体400还包括填充于堆叠半导体封装体410和420之间的空间中的底填构件460，例如非导电胶（NCP）或非导电膜（NCF）。
第一半导体封装体410包括半导体芯片412，具有前表面和与前表面相反的背表面；贯穿电极414，在半导体芯片412中形成为穿过前表面和背表面，并具有设置于前表面上的第一端和设置于背表面上的第二端；前侧凸块416，形成于贯穿电极414的第一端上；以及背侧凸块418，形成于贯穿电极414的第二端上。凸块416和418可配置为连接构件。而且，第一半导体封装体410还包括绝缘图案419，以暴露该贯穿电极414的第二端的方式形成于背表面上。
背侧凸块418包括埋入图案418a和导电图案418c，埋入图案418a设置于贯穿电极414的第二端的一部分上，导电图案418c设置于埋入图案418a以及贯穿电极414的第二端的其余部分上。导电图案418c可具有凸起的截面形状。埋入图案418a可设置于贯穿电极414的第二端的暴露部分的中间部分上。
在一个实施例中，背侧凸块418还包括插设于贯穿电极414的第二端和埋入图案418a之间以及贯穿电极414的第二端和导电图案418c之间的籽晶金属418b。埋入图案418a可由与籽晶金属418b实质类似和/或相同的金属形成，而导电图案418c由通过使用籽晶金属418b和埋入图案418a作为籽晶而生长的电镀层构成。
在另一实施例，虽然未示出于图中，但凸块418还包括插设于贯穿电极414的第二端和导电图案418c之间以及埋入图案418a和导电图案418c之间的籽晶金属418b。埋入图案418a是由电介质物质形成，导电图案418c是由通过使用籽晶金属418b作为籽晶而生长的电镀层构成。
至少一第二半导体封装体420堆叠于第一半导体封装体410上。在本实施例中，一个第二半导体封装体420被堆叠。第二半导体封装体420具有与第一半导体封装体410实质类似和/或相同的构型。具体地，第二半导体封装体420的背侧凸块418例如是经由诸如焊料的连接构件450与下面的第一半导体封装体410的前侧凸块416电性连接。
虽然未示出于图中，但可以堆叠至少两个第二半导体封装体，例如半导体封装体420。当堆叠至少两个第二半导体封装体420时，连接构件450可插设于之间并且使位置较高的半导体封装体的背侧凸块418与位置较低的半导体封装体的前侧凸块416电性连接。
根据本实施例的堆叠半导体封装体400还包括第三半导体封装体430，其堆叠于第二半导体封装体420上或堆叠的第二半导体封装体410、420当中位置最上的第二半导体封装体420上。除了前侧凸块没有形成于贯穿电极414的第一端之外，第三半导体封装体430可具有与第一半导体封装体410和第二半导体封装体420实质类似和/或相同的构型。也就是，第三半导体封装体430的背侧凸块418通过连接构件450与下面的第二半导体封装体420的前侧凸块电性连接。
第三半导体封装体430可包括与第一半导体封装体410和第二半导体封装体420实质类似和/或相同类型的半导体芯片，或者第三半导体封装体430可包括与第一半导体封装体410和第二半导体封装体420不同类型的半导体芯片，例如驱动芯片。
根据本实施例的堆叠半导体封装体400还包括结构体，其设置于第一半导体封装体410下方。
结构体可为第四半导体封装体440，第四半导体封装体440具有作为连接电极的贯穿电极444和前侧凸块446，如图4所示。第四半导体封装体440包括半导体芯片442，半导体芯片442具有前表面和与前表面相反的背表面；及贯穿电极444，形成为穿过前表面和背表面并且具有设置于前表面上的第一端和设置于背表面上的第二端。第四半导体封装体440还可包括前侧凸块446以及重分配线448，前侧凸块446形成于贯穿电极444的第一端上，重分配线448形成于半导体芯片442的背表面上使得重分配线448的端部与贯穿电极444的第二端相连。第四半导体封装体440可包括与第一半导体封装体410、第二半导体封装体420、及第三半导体封装体430实质类似和/或相同或不同类型的存储器芯片。
结构体可为具有连接电极（诸如接合指）的印刷电路板470，如图5所示。印刷电路板470包括设置于其上表面上作为连接电极的接合指472以及设置于其下表面上的球焊盘474。
虽然未示出于图中，但结构体可为具有连接电极的插入体。
根据本实施例的堆叠半导体封装体400还包括外部连接端子490，如焊料球，其附着于第四半导体封装体440的重分配线448上，如图4所示。
根据本实施例的堆叠半导体封装体400还可包括模制构件480，其形成于印刷电路板470的上表面上，以覆盖堆叠的第一半导体封装体410、第二半导体封装体420、及第三半导体封装体430。模制构件480可形成于诸如焊料球的外部连接端子490上方，外部连接端子490附着于设置在印刷电路板470的下表面上的球焊盘474，如图5所示。
在根据本实施例的堆叠半导体封装体中，背侧凸块由于存在埋入图案而具凸起的截面形状，因此不会出现凸块凹陷现象。因此，当堆叠第一、第二、及第三半导体封装体或当堆叠第二半导体封装体时，诸如NCP或NCF的底填构件陷入背侧凸块中的失效不会出现。
结果，在根据本实施例的堆叠半导体封装体中，由于半导体封装体之间的接合强度没有降低并且没有导致失效，因此可显著改善堆叠半导体封装体的特性和可靠性。
图6是示出包括依据本发明的半导体封装体的电子设备的立体图。
参照图6，根据本发明实施例的半导体封装体可由电子设备1000（例如：一移动电话）实施。由于根据本发明的实施例的半导体封装体实现良好的安装可靠性，在改善电子设备1000的特性方面提供优点。电子设备1000并不限于图6所示的移动电话，也可包括各种电子设备，诸如移动电子设备、膝上型电脑、笔记本电脑、便携式多媒体播放器（PMP）、MP3播放器、可携式摄像机，网路写字板、无线电话、导航仪、个人数字助理（PDA）等等。
图7是示出包括依照本发明的半导体封装体的电子系统的示例的方框图。
参照图7，电子系统700可包括控制器710、输入/输出单元720、及存储器730。控制器710、输入/输出单元720、及存储器730可通过总线750相互耦合。总线750可以使数据通过其移动的路径。
例如，控制器710可包括至少一微处理器、至少一数字信号处理器、至少一微控制器、及能够执行与前述元件相同功能的逻辑装置中的至少任意一种。控制器710与存储器730可包括根据本发明实施例的半导体封装体。
输入/输出单元720可包括选自小键板、键盘、显示器等当中的至少一种。
存储器730是用以储存数据的元件。存储器730可储存数据和/或控制器710要执行的指令等。存储器730可包括易失性存储装置和/或非易失性存储装置。而且，存储器730可由闪存形成。例如，应用了本发明技术的闪存可安装于诸如移动设备或桌上型电脑的信息处理系统。闪存可由固态驱动器（SSD）构成。在此情况下，电子系统700可将大量的数据稳定地储存于闪存系统中。
电子系统700还可包括配置以传送数据到通信网路以及从通信网路接收数据的接口740。接口740可为有线或无线型。例如，接口740可包括天线或有线或无线收发器。
此外，虽然未示于图中，但本领域技术人员将容易理解电子系统700可附加提供有应用芯片集、相机图像处理器（CIP）、及输入/输出装置等。
虽然本发明的具体实施例仅用于示例目的，然而本领域技术人员将理解，在不偏离所附权利要求揭示的本发明的范围与精神的情况下，各种修改、添加、及替代是可能的。
本申请要求2012年5月3日提交韩国知识产权局的韩国专利申请第10-2012-0047060号的优先权，其全部内容引用结合于此。

Claims (20)

1.一种半导体芯片，包括形成在焊垫上方、作为连接至外部电路的连接构件的凸块，该凸块包括：
埋入图案，形成在该焊垫的一部分上方；及
导电图案，形成在该埋入图案和该焊垫的其余部分上方且具有凸起的截面形状。
2.如权利要求1所述的半导体芯片，还包括：
绝缘图案，以暴露该焊垫的方式形成在该半导体芯片上方。
3.如权利要求1所述的半导体芯片，其中该埋入图案设置于该焊垫的中间部分上方。
4.如权利要求1所述的半导体芯片，还包括：
籽晶金属，设置在该焊垫和该埋入图案之间以及该焊垫和该导电图案之间。
5.如权利要求4所述的半导体芯片，其中该埋入图案由与该籽晶金属相同类型的金属形成。
6.如权利要求4所述的半导体芯片，其中该导电图案包括通过使用该籽晶金属和该埋入图案作为籽晶而生长的电镀层。
7.如权利要求1所述的半导体芯片，还包括：
籽晶金属，设置在该焊垫和该导电图案之间以及该埋入图案和该导电图案之间。
8.如权利要求7所述的半导体芯片，其中该埋入图案由电介质物质形成。
9.如权利要求7所述的半导体芯片，其中该导电图案包括通过使用该籽晶金属作为籽晶而生长的电镀层。
10.如权利要求1所述的半导体芯片，其中该焊垫包括接合焊垫或重分配焊垫。
11.一种半导体封装体，包括：
半导体芯片，具有前表面和背表面；
贯穿电极，在该半导体芯片中形成为穿过该前表面和该背表面，并具有设置于该前表面上的第一端和设置于该背表面上的第二端；以及
背侧凸块，形成于该贯穿电极的第二端上方，包括形成在该贯穿电极的第二端的一部分上方的埋入图案和形成在该埋入图案和该贯穿电极的第二端的其余部分上方的导电图案，并且具有凸起的截面形状。
12.如权利要求11所述的半导体封装体，还包括：
绝缘图案，以暴露该贯穿电极的第二端的方式形成于该半导体芯片的背表面上方。
13.如权利要求11所述的半导体封装体，还包括：
形成在该贯穿电极的第一端上方的前侧凸块。
14.权利要求11所述的半导体封装体，其中该埋入图案设置于该贯穿电极的暴露的第二端的中间部分上方。
15.如权利要求11所述的半导体封装体，其中该背侧凸块还包括:
籽晶金属，插设在该贯穿电极的第二端和该埋入图案之间以及该贯穿电极的第二端和该导电图案之间。
16.如权利要求15所述的半导体封装体，其中该埋入图案由与该籽晶金属相同类型的金属形成。
17.如权利要求11所述的半导体封装体，其中该导电图案包括通过使用该籽晶金属和埋入图案作为籽晶而生长的电镀层。
18.如权利要求11所述的半导体封装体，还包括：
籽晶金属，插设在该贯穿电极的第二端和该导电图案之间以及该埋入图案和该导电图案之间。
19.如权利要求18所述的半导体封装体，其中该埋入图案由电介质物质形成。
20.如权利要求18所述的半导体封装体，其中该导电图案包括通过使用籽晶金属作为籽晶而生长的电镀层。
CN2013100651826A 2012-05-03 2013-03-01 半导体芯片及半导体封装体 Pending CN103383928A (zh)

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