CN101335264A - 芯片堆叠结构及其制造方法 - Google Patents

芯片堆叠结构及其制造方法 Download PDF

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Publication number
CN101335264A
CN101335264A CNA2008101274893A CN200810127489A CN101335264A CN 101335264 A CN101335264 A CN 101335264A CN A2008101274893 A CNA2008101274893 A CN A2008101274893A CN 200810127489 A CN200810127489 A CN 200810127489A CN 101335264 A CN101335264 A CN 101335264A
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chip
connection pads
oxidation layer
anti oxidation
coupling assembling
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CNA2008101274893A
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CN101335264B (zh
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郑冲耕
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DB HiTek Co Ltd
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Dongbu Electronics Co Ltd
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Abstract

一种芯片堆叠结构及其制造方法，该芯片堆叠结构可以包括第一芯片，其包含第一半导体器件和电连接至第一半导体器件的第一连接焊盘；堆叠在第一芯片上的第二芯片，该第二芯片包括第二半导体器件和电连接至第二半导体器件的第二连接焊盘；以及连接组件，其介于第一连接焊盘和第二连接焊盘之间以将第一连接焊盘电连接至第二连接焊盘。该连接组件相比于芯片未被堆叠时具有更低的电阻，从而提供了高可靠性和高性能。

Description

芯片堆叠结构及其制造方法
基于35 U.S.C§119，本申请要求于2007年6月29日提交的第10-2007-0065058号韩国专利申请的优先权，其全部内容结合于此作为参考。
技术领域
本发明涉及一种半导体器件，更具体地，涉及一种芯片堆叠结构(chip stacked structure)及其制造方法。
背景技术
目前的便携式电子产品市场已经经历了显著的增长。为了满足这样的增长，有必要制造高集成度的部件(即薄、短、小)用于安置在系统上和/或上方。为了在部件中实现这样的尺寸需求，用于减小作为安装部件的半导体封装(package)的单个尺寸的技术可以使用片上系统(SOC)方法和系统封装(system-in-package)方法，其中片上系统方法将多个单独的半导体芯片制造成单一芯片而系统封装方法将多个半导体芯片集成为单一封装。
发明内容
本发明的实施例涉及一种芯片堆叠结构及其制造方法，其已经增强了芯片间的粘合度并提高产量和可靠性。
本发明的实施例涉及一种芯片堆叠结构，其包括以下至少之一：第一芯片，其包含第一半导体器件和电连接至该第一半导体器件的第一连接焊盘(connection pad)；堆叠在第一芯片上和/或上方的第二芯片，其包括第二半导体器件和电连接至该第二半导体器件并面向第一连接焊盘的第二连接焊盘；以及在第一连接焊盘和第二连接焊盘之间插入的连接组件以电连接第一连接焊盘和第二连接焊盘。
本发明的实施例涉及一种制造芯片堆叠结构的方法，其包括以下步骤中的至少一个：在包括第一半导体器件的第一芯片上和/或上方放置电连接至第一连接焊盘(该第一连接焊盘为电连接至第一半导体器件)的连接组件；然后在第一芯片和该连接组件的表面上和/或上方形成抗氧化层；然后移除该抗氧化层；然后在包含第二半导体器件和第二连接焊盘(其电连接到该第二半导体器件)的第二芯片上和/或上方放置第一芯片和连接组件，并且将第二连接焊盘和该焊盘进行电连接。
本发明的实施例涉及一种制造芯片堆叠结构的方法，其包括以下步骤中的至少一个：形成第一芯片，其具有第一连接焊盘和电连接至该第一连接焊盘的第一半导体器件；然后在第一连接焊盘的暴露末端上放置连接组件并电连接至第一连接焊盘；然后在第一芯片和连接组件暴露的表面上形成抗氧化层；然后形成第二芯片，其具有第二连接焊盘和电连接至该第二连接焊盘的第二半导体器件；然后操作第一芯片和第二芯片中的至少一个以便连接组件的暴露的表面朝向第二连接焊盘；然后移除抗氧化层；然后通过将连接组件连接到第二连接焊盘将第一芯片电连接至第二芯片。
本发明的实施例涉及一种方法，其可以包括以下步骤中的至少一个：设置第一芯片和第二芯片，其中第一芯片具有与在该第一芯片上形成的第一半导体器件电连接的第一连接焊盘而第二芯片具有与在该第二芯片上形成的第二半导体器件电连接的第二连接焊盘；然后在第一连接焊盘上放置连接组件并且该连接组件与第一连接焊盘电连接；然后在第一芯片和连接组件的暴露的表面上形成抗氧化层；然后通过将该抗氧化层暴露到溶剂混合物以去除该抗氧化层；然后通过将连接组件连接到第二连接焊盘以使第一芯片电连接至第二芯片。
附图说明
图1到图5示出了根据本发明的实施例的芯片堆叠结构及制造芯片堆叠结构的方法。
具体实施方式
如示例图1中所示，芯片堆叠结构可包含第一芯片100、第二芯片200以及介于第一芯片100和第二芯片200之间用于将第一芯片100连接到第二芯片200的连接组件300。第一芯片100可以包括：第一硅片110、第一半导体器件120、第一介电层131、第一垂直互连结构141、第一水平互连结构151、第二介电层132、第二垂直互连结构142、第二水平互连结构152、第三介电层133、第一穿透电极(through electrode)160和第一连接焊盘161。作为第一硅片110所用材料的实例，其可以是单晶硅等。第一硅片110可具有诸如盘状的形状。
可在第一硅片110上和/或上方形成多个相隔开的第一半导体器件120。第一半导体器件120可以是(例如)，CMOS晶体管、双扩散MOS(DMOS)晶体管、晶体管、电容器、以及双极连接晶体管。第一介电薄膜131可以形成在第一硅片110上和/或上方并覆盖第一半导体器件120。第一垂直互连结构141可以穿透第一介电层131而形成并电连接至第一半导体器件120。作为第一垂直互连结构141所用材料的实例，其可以是诸如铜(Cu)，铝(Al)、钛(Ti)、钨(W)和铁(Fe)等金属。第一水平互连结构151可以形成在第一介电层131上和/或上方并电连接至第一垂直互连结构141。作为第一水平互连结构151所用材料的实例，其可以是诸如铜(Cu)，铝(Al)、钛(Ti)、钨(W)和铁(Fe)等金属。
第二介电层132可以形成在第一介电层131上和/或上方并覆盖第一水平互连结构151。可以穿透第二介电层132而形成第二垂直互连结构142并将其电连接至第二水平互连结构152。可以在第二介电层132上和/或上方形成第二水平互连结构152并将其电连接至第二垂直互连结构142。可以在第二介电层132上和/或上方形成第三介电层133并且该第三介电层覆盖第二水平互连结构152。
可以穿透第一硅片110、第一介电层131、第二介电层132、以及第三介电层133来形成第一穿透电极160。作为第一穿透电极160所用材料的实例，其可以是诸如铜、钨、和铝等金属。可选地，可穿透第一芯片100的一部分来形成第一穿透电极160。例如，可以穿透部分第一硅片110、第一介电层131和第二介电层132来形成第一穿透电极。
可以在第一穿透电极160的一个暴露末端或两个暴露末端上和/或上方设置第一连接焊盘161。可以通过第一垂直互连结构141、第一水平互连结构151、第二垂直互连结构142、第二水平互连结构152和第一穿透电极160将第一半导体器件120电连接至第一连接焊盘161。因此，通过第一连接焊盘161可将来自(多个)外部设备施加的信号施加到第一半导体器件120。依次地，通过第一连接焊盘161可将存储在第一半导体器件120中的信号施加到(多个)外部设备。可选地，第一连接焊盘161可以电连接至第一穿透电极160并可以形成在第一芯片100上和/或上方。第一连接焊盘161可以电连接至第一穿透电极160以便其电连接至第一半导体器件120。
可间隔放置第二芯片200，其具有与第一芯片100暴露的表面间隔预定距离L的暴露的表面。间隔L可以是在大约4μm到6μm的范围内。第二芯片200可被间隔放置以便第一连接焊盘161和第二芯片的第二连接焊盘261彼此相对。第二芯片200可以包括：第二硅片210，第二半导体器件220，第四介电层231，第三垂直互连结构241，第三水平互连结构251，第五介电层232，第四垂直互连结构242，第四水平互连结构252，第六介电层233，第二穿透电极260和第二连接焊盘261。作为第二硅片210所用材料的实例，其可以是单晶硅等。第二硅片210可具有诸如盘状的形状。
可以在第二硅片210上和/或上方形成多个第二半导体器件220。第二半导体器件220可以是(例如)，CMOS晶体管、双扩散MOS(DMOS)晶体管、晶体管、电容器、以及双极连接晶体管。可以在第一硅片210上和/或上方形成第四介电层231并且该第四介电层覆盖第一半导体器件220。可以穿透第四介电层231来形成第三垂直互连结构241并将其电连接至第二半导体器件220。作为第三垂直互连结构241所用材料的实例，其可以是诸如铜(Cu)、铝(Al)、钛(Ti)、钨(W)和铁(Fe)等金属。可以在第四介电层231上面和/或上方形成第三水平互连结构251并将其电连接至第三垂直互连结构241。作为第三水平互连结构251所用材料的实例，其可以是诸如铜(Cu)、铝(Al)、钛(Ti)、钨(W)、以及铁(Fe)等金属。
可以在第四介电层231上和/或上方形成第五介电层232并且该第五介电层覆盖第三水平互连结构251。可以穿透第五介电层232来形成第四垂直互连结构242并将其电连接至第三水平互连结构251。可以穿透第五介电层232来形成第四水平互连结构252并将其电连接至第四垂直互连结构242。
可以在第五介电层232上和/或上方形成第六介电层233并且该第六介电层覆盖第四水平互连结构252。可以穿透第二硅片210、第四介电层231、第五介电层232和第六介电层233来形成第二穿透电极260。作为第二穿透电极260所用材料的实例，其可以是诸如铜、钨、铝等金属。可选地，可以穿透第二芯片200的一部分来形成第二穿透电极260。例如，可以穿透一部分第二硅片210、第四介电层231和第五介电层232来形成第二穿透电极260。
可以在第二穿透电极260的一个暴露末端或两个暴露末端上和/或之上设置第二连接焊盘261。可以通过第三垂直互连结构241、第三水平互连结构251、第四垂直互连结构242、以及第二穿透电极260将第二半导体器件220电连接到第二连接焊盘261。因此，通过第二连接焊盘261可将从(多个)外部设备施加的信号施加到第二半导体器件220。依次地，通过第二连接焊盘261可将存储在第二半导体器件220中的信号施加到(多个)外部设备。可选地，可以将第二连接焊盘261电连接至第二穿透电极260并可形成在第二芯片100上和/或上方。可以将第二连接焊盘261电连接至第二穿透电极260以便其电连接至第二半导体器件220。
可以在第一芯片100和第二芯片200之间插入连接组件300。可以在第一连接焊盘161和第二连接焊盘261之间插入连接组件300以接触第一连接焊盘161和第二连接焊盘261。可以将连接组件300电连接至第一连接焊盘161和第二连接焊盘261。连接组件300可具有(例如)柱形(矩形)形状或球形(圆形)形状。连接组件300可具有高度在大约4μm到6μm范围内的柱状形状。连接组件300可具有直径在大约4μm到6μm范围内的球形形状。连接组件300可以是具有厚度在大约4μm到6μm范围内的焊膏(solderpaste)。
可以通过放置在第一芯片100和第二芯片200最外表面上和/或之上的固定组件(fixing member)和/或在第一芯片100和第二芯片200之间插入的粘合剂来将第一芯片100、第二芯片200以及连接组件300相互连接。
根据示例图1中所示的实施例的上述的芯片堆叠结构可以有堆叠在两个层中的芯片。可是，实施例并不局限于此。例如，芯片堆叠结构可以有堆叠在多于三个层中的多个芯片。在这种情况下，可以按照与示例图1中所示芯片100和200相同的形式以及本文中所描述的来堆叠多于三个的芯片。
示例图2到图5示出了根据本发明的实施例制造芯片堆叠结构的方法
如示例图2中所示，可以形成第一芯片100并可在连接焊盘161上和/或上方放置连接组件300。为了形成第一芯片100，在第一硅片110上和/或上方形成第一半导体器件120。然后可以在包含第一半导体器件120的第一硅片110上和/或上方形成第一介电层131。然后可通过掩模工艺蚀刻第一介电层131以形成多个暴露第一半导体器件120的第一通孔(via hole)。然后可将第一通孔填充金属材料以形成第一垂直互连结构141。在形成第一垂直互连结构141之后，可形成覆盖第一介电层131的金属层。然后可通过掩模工艺图样化该金属层以形成第一水平互连结构151。在形成第一水平互连结构151之后，可以在第一介电层131上和/或上方形成覆盖第一水平互连结构151的第二介电层132。然后可通过掩模工艺来蚀刻第二介电层132以形成多个暴露第一水平互连结构151的第二通孔。可将该第二通孔填充金属材料以形成第二垂直互连结构142。
在形成第二垂直互连结构142之后，可以形成覆盖第二介电层132的金属层。然后可以通过掩模工艺图样化该金属层以形成第二水平互连结构152。在形成第二水平互连结构152之后，可以在第二介电层132上和/或上方形成覆盖第二水平互连结构152的第三介电层133。在形成第三介电层133后，然后可以穿透至少部分第一硅片110、第一介电层131、第二介电层132和第三介电层133来形成第三通孔。然后可将第三通孔填充金属材料。可以在水平方向上切割第一硅片110以形成第一穿透电极160。此时，第一穿透电极160的两末端均被暴露以便暴露末端形成第一连接焊盘161。作为使用的金属材料的实例，其可以是铜、钨和铝等。可以形成第一穿透电极160以电连接至第二水平互连结构152的至少一部分。
在形成第一芯片100之后，可以在穿透电极160的暴露末端上和/或上方布置连接组件300。连接组件300可以由诸如金属的导电材料组成。用于连接组件300的材料的实例可以是铜、铝、银、锌、金、钛、钨和钼(Mo)等。连接组件300可具有柱形，球形或焊膏形。连接组件300可以是高度在大约4μm到6μm的柱形或是直径在大约4μm到6μm的球形。连接组件300可以是厚度在4μm到6μm的焊膏。
如示例图3所示，在将连接件300布置在第一连接焊盘161上和/或上方之后，可以在第一芯片100和连接组件300的暴露表面上和/或上方形成抗氧化层170。可通过在约50℃到200℃的温度范围内和约10mTorr到500mTorr的压力下实施了5分钟到10分钟的等离子增强型化学汽相沉积(PECVD)在第一芯片100和连接组件300的暴露表面的上和/或上方放置抗氧化材料来形成抗氧化层170。抗氧化层170可以由聚合材料组成。抗氧化层170可以由诸如环己烷基树脂(cyclohexane based resin)、丙烯酸基树脂(acrylicbased resin)、聚酰亚胺(polyimide)、苯并环丁烯(benzocyclobutene)、聚苯并噁唑(polybenzoxazol)、环氧树脂(epoxy resin)和酚基树脂(phenol based resin)中的至少一种组成。
如示例图4中所示，接下来可形成第二芯片200。为了形成第二芯片200，可以在第二硅片210上和/或上方形成第二半导体器件220。然后可以在包含第二半导体器件220的第二硅片210上和/或上方形成第四介电层231。接下来，可以通过掩模工艺来蚀刻第四介电层231以形成多个暴露第二半导体器件220的第四通孔。然后可将第四通孔填充金属材料以形成第三垂直互连结构241。在形成第三垂直互连结构241之后，可形成覆盖第四介电层231的金属层。可通过掩模工艺来图样化该金属层以形成第三水平互连结构251。在形成第三水平互连结构251之后，可以在第四介电层231上和或上方形成覆盖第三水平互连结构251的第五介电层232。然后可以通过掩模工艺来蚀刻第五介电层232以形成多个暴露第三水平互连结构251的第五通孔。接下来，可将第五通孔填充金属材料以形成第四垂直互连结构242。
在形成第四垂直互连结构242之后，可形成覆盖第五介电层232的金属层。接下来，可以通过掩模工艺来图样化该金属层以形成第四水平互连结构252。在形成第四水平互连结构252之后，可以在第五介电层232上和/或上方形成覆盖第四水平互连结构252的第六介电层233。在形成第六介电层233之后，可以穿透至少部分第二硅片210，第四介电层231，第五介电层232和第六介电层233来形成第六通孔。可将第六通孔填充金属材料。可以在水平方向上切割第二硅片210以形成第二穿透电极260。接下来可以暴露第二穿透电极260的两末端以便所暴露的末端可以形成第二连接焊盘261。作为所用金属的材料的实例，其可以是铜、钨、以及铝等。可形成第二穿透电极260以电连接至第四水平互连结构252的至少一部分。
在形成第二芯片200之后，可布置连接组件300和第二连接焊盘261使其彼此相对。其后，可以喷射抗氧化层去除剂以去除抗氧化层170。抗氧化层去除剂可以包括(例如)，四甲基氢氧化物(tetramethylhydroxide，TMH)，过氧化氢和水的至少一种。抗氧化层去除剂可以包括浓度在约2.0mol％到3.0mol％范围内的TMH、浓度在约5.0mol％到6.0mol％范围内的过氧化氢以及浓度在约91.0mol％到93.0mol％范围内的水中的至少一种。抗氧化层去除剂可选择性地包括氟化铵(ammonium fluoride，NH4F)、硼氢化氟(boronhydro fluoride，BHF)、过氧化氢和水中的至少一种。抗氧化层去除剂可选择性地包括硫酸和水中的至少一种。可将抗氧化层去除剂喷射在第一芯片100和连接组件300上和/或上方以去除抗氧化层170。抗氧化层去除剂同时从第一芯片100和连接组件300表面去除外来杂质。抗氧化层去除剂也同时与凸出自第一硅片110表面和金属表面的部分反应以去除该凸出部分。换句话说，该抗氧化层去除剂也可用来降低第一芯片100和连接组件300的表面粗糙程度。
然后操作第一芯片100和第二芯片200以使连接组件300与第二连接焊盘261相接触。从而，第一穿透电极160和第二穿透电极260通过连接组件300电连接。
根据本发明的实施例的芯片堆叠结构布置芯片以使连接焊盘彼此相对并在连接焊盘之间插入与上部芯片和下部芯片电连接的连接组件。因此，该连接组件具有宽于连接焊盘平面的横截面和等于芯片间的空间间隔的长度。从而，相比于不堆叠芯片或连接焊盘不彼此相对时，根据实施例的连接件可具有更低的电阻。由于电阻较低，因此根据本发明实施例的芯片堆叠结构可具有高可靠性和高性能。而且，可以堆叠多个芯片以便相比于芯片被水平放置时该堆叠芯片可更强有力地抵抗外部的物理冲击。
根据本发明实施例的制造芯片堆叠结构的方法可以在芯片和连接组件的表面上形成抗氧化层。该抗氧化层而可用来防止在制造过程期间芯片和连接组件的金属的氧化。因此，相比于未形成抗氧化层时，该制造芯片堆叠结构的方法可以降低连接组件的阻值。根据实施例的方法也可以提高产量。可以使用抗氧化层去除剂以从芯片和连接组件表面去除不需要的材料。该抗氧化层去除剂可以降低芯片和连接组件的表面粗糙程度。
尽管本文中描述了多个实施例，但是应该理解，本领域技术人员可以想到多种其他修改和实施例，它们都将落入本公开的原则的精神和范围内。更特别地，在本公开、附图、以及所附权利要求的范围内，可以在主题结合排列的排列方式和/或组成部分方面进行各种修改和改变。除了组成部分和/或排列方面的修改和改变以外，可选的使用对本领域技术人员来说也是显而易见。

Claims (20)

1.一种装置，包括：
第一芯片，其包括第一半导体器件和电连接至所述第一半导体器件的第一连接焊盘；
第二芯片，其堆叠在所述第一芯片上，所述第二芯片包括第二半导体器件和电连接至所述第二半导体器件的第二连接焊盘；以及
连接组件，其介于所述第一连接焊盘和所述第二连接焊盘之间以将所述第一连接焊盘电连接至所述第二连接焊盘。
2.根据权利要求1所述的装置，其中，所述第一芯片和所述第二芯片之间的空间间隔在4μm至6μm范围内。
3.根据权利要求1所述的装置，进一步包括第一穿透电极，所述第一穿透电极穿透所述第一芯片的至少一部分。
4.根据权利要求1所述的装置，进一步包括第二穿透电极，所述第二穿透电极穿透所述第二芯片的至少一部分。
5.根据权利要求1所述的装置，其中，所述连接组件具有4μm至6μm范围内的直径。
6.根据权利要求1所述的装置，其中，所述连接组件具有4μm至6μm范围内的高度。
7.根据权利要求1所述的装置，其中，所述连接组件具有4μm至6μm范围内的厚度。
8.一种方法，包括：
形成第一芯片，其具有第一连接焊盘和电连接至所述第一连接焊盘的第一半导体器件；
然后，在所述第一连接焊盘的暴露末端上放置连接组件并且电连接至所述第一连接焊盘；
然后，在所述第一芯片和所述连接组件的暴露表面上形成抗氧化层；
然后，形成第二芯片，其具有第二连接焊盘和电连接至所述第二连接焊盘的第二半导体器件；
然后，对所述第一芯片和所述第二芯片中的至少一个进行操作以便所述连接组件的暴露表面朝向所述第二连接焊盘；
然后，去除所述抗氧化层；以及
通过将所述连接组件连接至所述第二连接焊盘以使所述第一芯片电连接至所述第二芯片。
9.根据权利要求8所述的方法，其中，形成所述抗氧化层包括通过PECVD工艺在所述第一芯片和所述连接组件的暴露表面上形成聚合材料。
10.根据权利要求9所述的方法，其中，所述PECVD工艺是在50℃至200℃的温度范围、10mTorr至500mTorr的压力范围以及5分钟至10分钟的时间范围所实施的。
11.根据权利要求10所述的方法，其中，形成所述抗氧化层包括通过PECVD工艺在所述第一芯片和所述连接组件的暴露表面上形成环己烷基树脂、丙烯酸基树脂、聚酰亚胺、苯并环丁烯、聚苯并噁唑、环氧树脂和酚基树脂的至少一种。
12.根据权利要求11所述的方法，其中，所述PECVD工艺是在50℃至200℃的温度范围、10mTorr至500mTorr的压力范围以及5分钟至10分钟的时间范围所实施的。
13.根据权利要求10所述的方法，其中，去除所述抗氧化层包括将所述抗氧化层暴露在抗氧化层去除剂混合物中，所述抗氧化层去除剂混合物包括四甲基氢氧化物、过氧化氢和水的至少一种。
14.根据权利要求10所述的方法，其中，去除所述抗氧化层包括将所述抗氧化层暴露在抗氧化层去除剂混合物中，所述抗氧化层去除剂混合物包括浓度在2.0mol％至3.0mol％范围内的四甲基氢氧化物，浓度在5.0mol％至6.0mol％范围内的过氧化氢以及浓度在91.0mol％至93.0mol％范围内的水。
15.根据权利要求10所述的方法，其中，去除所述抗氧化层包括将所述抗氧化层暴露在抗氧化层去除剂混合物中，所述抗氧化层去除剂混合物包括硫酸和水的至少一种。
16.一种方法，包括：
设置第一芯片，其具有电连接至形成在所述第一芯片上的第一半导体器件的第一连接焊盘，以及设置第二芯片，其具有电连接至形成在所述第二芯片上的第二半导体器件的第二连接焊盘；
然后，在所述第一连接焊盘上放置连接组件并且所述连接组件电连接至所述第一连接焊盘；
然后，在所述第一芯片和所述连接组件的暴露表面上形成抗氧化层；
然后，通过将所述抗氧化层暴露在溶剂混合物中来去除所述抗氧化层；以及
通过将所述连接组件连接至所述第二连接焊盘以使所述第一芯片电连接至所述第二芯片。
17.根据权利要求16所述的方法，其中，所述溶剂混合物包括硫酸和水的至少一种。
18.根据权利要求16所述的方法，其中，所述溶剂混合物包括四甲基氢氧化物，过氧化氢和水的至少一种。
19.根据权利要求16所述的方法，其中，所述溶剂混合物包括浓度在2.0mol％至3.0mol％范围内的四甲基氢氧化物、浓度在5.0mol％至6.0mol％范围内的过氧化氢以及浓度在91.0mol％至93.0mol％范围内的水。
20.根据权利要求16所述的方法，其中，形成所述抗氧化层包括在所述第一芯片和所述连接组件的暴露表面上形成聚合材料。
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