JP5621621B2 - 半導体装置と半導体装置の製造方法 - Google Patents
半導体装置と半導体装置の製造方法 Download PDFInfo
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- JP5621621B2 JP5621621B2 JP2011012325A JP2011012325A JP5621621B2 JP 5621621 B2 JP5621621 B2 JP 5621621B2 JP 2011012325 A JP2011012325 A JP 2011012325A JP 2011012325 A JP2011012325 A JP 2011012325A JP 5621621 B2 JP5621621 B2 JP 5621621B2
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- 239000004065 semiconductor Substances 0.000 title claims description 82
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 238000000034 method Methods 0.000 title description 5
- 239000000758 substrate Substances 0.000 claims description 35
- 238000005530 etching Methods 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 8
- 230000003213 activating effect Effects 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 238000011109 contamination Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Description
図1は本発明の実施の形態1に係る半導体装置の断面図である。本発明の実施の形態1に係る半導体装置は、LPT(Light Punch Through)構造のIGBT(Insulated Gate Bipolar Transistor)で形成されている。この半導体装置は、珪素によって形成された半導体基板10を備えている。半導体基板10の表面には表面構造12が形成されている。半導体基板10の裏面にはコレクタ電極14が形成されている。
図4は本発明の実施の形態2に係る半導体装置の断面図である。本発明の実施の形態2に係る半導体装置は、本発明の実施の形態1に係る半導体装置と、n型バッファ層を有しない点において相違する。図5は図4のV−V´破線におけるキャリア濃度を示す図である。n型バッファ層を有しない構成においても、p型コレクタ層28のキャリア濃度ピーク位置をコレクタ電極14から1μm以上離れた位置にすることで、上述の本発明の効果を得ることができる。
図6は本発明の実施の形態3に係る半導体装置の製造方法を示すフローチャートである。本発明の実施の形態3に係る半導体装置の製造方法は図6に沿って説明する。まず、半導体基板の表面に表面構造を形成する(ステップ60)。図7はステップ60により半導体基板80の表面に表面構造12を形成したことを示す断面図である。表面構造12の詳細は上述したとおりである。
Claims (6)
- キャリア濃度が最大となるキャリア濃度ピーク位置が表面から1μm以上離れた位置にあるコレクタ層を有する半導体基板と、
前記コレクタ層の表面に接するように形成されたコレクタ電極と、を備え、
前記コレクタ層は、前記キャリア濃度ピーク位置と前記コレクタ電極との間に、前記キャリア濃度ピーク位置におけるキャリア濃度よりはキャリア濃度が低い第2のキャリア濃度ピーク位置を有することを特徴とする半導体装置。 - 前記キャリア濃度ピーク位置のキャリア濃度は1×1018[atoms/cm3]以下であることを特徴とする請求項1に記載の半導体装置。
- 前記第2のキャリア濃度ピーク位置は、前記コレクタ層のうち前記コレクタ電極に接する位置にあることを特徴とする請求項1に記載の半導体装置。
- 前記半導体基板はワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料、又はダイヤモンドであることを特徴とする請求項4に記載の半導体装置。
- 半導体基板の表面に表面構造を形成する工程と、
前記半導体基板の裏面にイオン注入を行う工程と、
前記イオン注入で注入されたドーパントをアニールにより活性化してコレクタ層を形成する工程と、
前記コレクタ層を形成する工程の後に、前記コレクタ層のうち前記アニールの際に外部に露出していた部分をエッチングする工程と、
前記エッチングする工程の後に、前記コレクタ層に接するようにコレクタ電極を形成する工程と、を備え、
前記コレクタ層を形成する工程では、前記コレクタ層のキャリア濃度が最大となるキャリア濃度ピーク位置は、前記半導体基板の裏面から1μm以上離れた位置にあり、
前記エッチングは前記キャリア濃度ピーク位置で停止することを特徴とする半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011012325A JP5621621B2 (ja) | 2011-01-24 | 2011-01-24 | 半導体装置と半導体装置の製造方法 |
US13/237,577 US8614448B2 (en) | 2011-01-24 | 2011-09-20 | Semiconductor device and method for manufacturing a semiconductor device having a maximal carrier concentration at multiple carrier concentration peak positions |
DE102011088624.9A DE102011088624B4 (de) | 2011-01-24 | 2011-12-14 | Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung |
KR1020120005054A KR101318219B1 (ko) | 2011-01-24 | 2012-01-17 | 반도체장치와 반도체장치의 제조방법 |
CN201210018534.8A CN102610634B (zh) | 2011-01-24 | 2012-01-20 | 半导体装置和半导体装置的制造方法 |
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JP2011012325A JP5621621B2 (ja) | 2011-01-24 | 2011-01-24 | 半導体装置と半導体装置の製造方法 |
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JP2012156207A JP2012156207A (ja) | 2012-08-16 |
JP2012156207A5 JP2012156207A5 (ja) | 2013-07-11 |
JP5621621B2 true JP5621621B2 (ja) | 2014-11-12 |
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US (1) | US8614448B2 (ja) |
JP (1) | JP5621621B2 (ja) |
KR (1) | KR101318219B1 (ja) |
CN (1) | CN102610634B (ja) |
DE (1) | DE102011088624B4 (ja) |
Families Citing this family (7)
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CN103918078B (zh) * | 2011-11-09 | 2016-09-14 | 丰田自动车株式会社 | 半导体装置及其制造方法 |
JP6265594B2 (ja) * | 2012-12-21 | 2018-01-24 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法、及び半導体装置 |
JP6219044B2 (ja) * | 2013-03-22 | 2017-10-25 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP6844130B2 (ja) * | 2015-08-18 | 2021-03-17 | 富士電機株式会社 | 半導体装置及びその製造方法 |
JP7119350B2 (ja) * | 2017-11-22 | 2022-08-17 | 富士電機株式会社 | 縦型GaN系半導体装置の製造方法および縦型GaN系半導体装置 |
JP7010184B2 (ja) * | 2018-09-13 | 2022-01-26 | 株式会社デンソー | 半導体装置 |
JP7249586B2 (ja) * | 2019-03-18 | 2023-03-31 | 国立大学法人東海国立大学機構 | 窒化物半導体装置の製造方法 |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4053924A (en) * | 1975-02-07 | 1977-10-11 | California Linear Circuits, Inc. | Ion-implanted semiconductor abrupt junction |
US4111720A (en) * | 1977-03-31 | 1978-09-05 | International Business Machines Corporation | Method for forming a non-epitaxial bipolar integrated circuit |
US4782379A (en) * | 1981-11-23 | 1988-11-01 | General Electric Company | Semiconductor device having rapid removal of majority carriers from an active base region thereof at device turn-off and method of fabricating this device |
US5270230A (en) | 1990-04-20 | 1993-12-14 | Fuji Electric Co., Ltd. | Method for making a conductivity modulation MOSFET |
JP2663679B2 (ja) | 1990-04-20 | 1997-10-15 | 富士電機株式会社 | 伝導度変調型mosfet |
US5264378A (en) | 1990-04-20 | 1993-11-23 | Fuji Electric Co., Ltd. | Method for making a conductivity modulation MOSFET |
JPH08288500A (ja) * | 1995-04-20 | 1996-11-01 | Hitachi Ltd | 炭化珪素半導体素子とその製造法及び用途 |
JP3727827B2 (ja) * | 2000-05-15 | 2005-12-21 | 株式会社東芝 | 半導体装置 |
WO2002061845A1 (en) | 2001-02-01 | 2002-08-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
DE10104776A1 (de) | 2001-02-02 | 2002-08-22 | Infineon Technologies Ag | Bipolartransistor und Verfahren zu dessen Herstellung |
JP4023773B2 (ja) | 2001-03-30 | 2007-12-19 | 株式会社東芝 | 高耐圧半導体装置 |
JP5160001B2 (ja) | 2001-04-02 | 2013-03-13 | 富士電機株式会社 | 半導体装置の製造方法 |
JP4967205B2 (ja) * | 2001-08-09 | 2012-07-04 | 富士電機株式会社 | 半導体装置の製造方法 |
JP2003249653A (ja) * | 2002-02-26 | 2003-09-05 | Fuji Electric Co Ltd | 半導体装置 |
JP3960174B2 (ja) * | 2002-09-09 | 2007-08-15 | 富士電機デバイステクノロジー株式会社 | 半導体装置の製造方法 |
JP2004311481A (ja) | 2003-04-02 | 2004-11-04 | Toshiba Corp | 半導体装置 |
JP4676708B2 (ja) * | 2004-03-09 | 2011-04-27 | 新電元工業株式会社 | 半導体装置の製造方法 |
JP2005354031A (ja) | 2004-05-13 | 2005-12-22 | Mitsubishi Electric Corp | 半導体装置 |
JP4415767B2 (ja) | 2004-06-14 | 2010-02-17 | サンケン電気株式会社 | 絶縁ゲート型半導体素子、及びその製造方法 |
JP2006210606A (ja) | 2005-01-27 | 2006-08-10 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
JP2006332199A (ja) * | 2005-05-24 | 2006-12-07 | Shindengen Electric Mfg Co Ltd | SiC半導体装置 |
JP2007123469A (ja) * | 2005-10-27 | 2007-05-17 | Toyota Central Res & Dev Lab Inc | 半導体装置とその製造方法 |
JP2007135252A (ja) * | 2005-11-08 | 2007-05-31 | Hitachi Ltd | 電力変換装置 |
JP4867518B2 (ja) * | 2006-08-03 | 2012-02-01 | 株式会社デンソー | 半導体装置の製造方法 |
JP4979309B2 (ja) * | 2006-08-29 | 2012-07-18 | 三菱電機株式会社 | 電力用半導体装置 |
JP5320679B2 (ja) | 2007-02-28 | 2013-10-23 | 富士電機株式会社 | 半導体装置およびその製造方法 |
WO2009099182A1 (ja) | 2008-02-06 | 2009-08-13 | Rohm Co., Ltd. | 半導体装置 |
JP2010056134A (ja) | 2008-08-26 | 2010-03-11 | Mitsubishi Electric Corp | 半導体装置 |
JP2010206111A (ja) | 2009-03-05 | 2010-09-16 | Toshiba Corp | 半導体装置 |
JP2011012325A (ja) | 2009-07-05 | 2011-01-20 | Bisansei Denkaisui Kenkyusho:Kk | 電解槽 |
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US20120187416A1 (en) | 2012-07-26 |
DE102011088624B4 (de) | 2016-06-02 |
KR20120085663A (ko) | 2012-08-01 |
CN102610634B (zh) | 2015-07-15 |
DE102011088624A1 (de) | 2012-07-26 |
KR101318219B1 (ko) | 2013-10-15 |
CN102610634A (zh) | 2012-07-25 |
US8614448B2 (en) | 2013-12-24 |
JP2012156207A (ja) | 2012-08-16 |
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