JP5590042B2 - 電子部品デバイスおよびパッケージ基板 - Google Patents
電子部品デバイスおよびパッケージ基板 Download PDFInfo
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- JP5590042B2 JP5590042B2 JP2011538384A JP2011538384A JP5590042B2 JP 5590042 B2 JP5590042 B2 JP 5590042B2 JP 2011538384 A JP2011538384 A JP 2011538384A JP 2011538384 A JP2011538384 A JP 2011538384A JP 5590042 B2 JP5590042 B2 JP 5590042B2
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- electronic component
- package substrate
- esd protection
- ground electrode
- protection element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Emergency Protection Circuit Devices (AREA)
- Structure Of Printed Boards (AREA)
- Elimination Of Static Electricity (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Description
図1および2に、本発明の第1の実施形態にかかる電子部品デバイスを示す。なお、図1はこの電子部品デバイスの断面図、図2はこの電子部品デバイスのESD保護素子部分を示す要部断面図である。
図3に、本発明の第2の実施形態にかかる電子部品デバイスを示す。なお、図3はこの電子部品デバイスの断面図である。
図4に、本発明の第3の実施形態にかかる電子部品デバイスを示す。なお、図4はこの電子部品デバイスの断面図である。
図5に、本発明の第4の実施形態にかかる電子部品デバイスを示す。なお、図5はこの電子部品デバイスの断面図である。
2:ESD保護素子
3:空洞部
4:混合部
4a:絶縁材料
4b:金属材料
5a、5b:放電電極
6:信号ライン
9:入出力電極
10:共通グランド電極
13、23:IC素子(電子部品素子)
15:封止樹脂
20:ESD保護素子専用グランド電極
21:電子部品素子専用グランド電極
25:上蓋
33:SAW素子(電子部品素子)
Claims (6)
- パッケージ基板に、電子部品素子を実装してなる電子部品デバイスにおいて、
前記パッケージ基板が、内部にESD保護素子を備え、
前記ESD保護素子が、少なくとも、前記パッケージ基板の内部に形成された空洞部と、前記空洞部内において対向して形成された一対の放電電極とで構成され、前記パッケージ基板の内部に形成された信号ラインと、前記パッケージ基板の表面に形成されたグランド電極との間に挿入されており、
前記グランド電極が、前記電子部品素子のグランド電極と別個のESD保護素子専用グランド電極であることを特徴とする電子部品デバイス。 - 前記ESD保護素子が、さらに、前記空洞部の底部に、金属材料と、前記パッケージ基板を構成する絶縁材料とを含む混合材料からなる混合部を備え、前記一対の放電電極が、前記混合部の上に形成されていることを特徴とする、請求項1に記載された電子部品デバイス。
- 前記電子部品素子がIC素子またはSAW素子であることを特徴とする、請求項1または2に記載された電子部品デバイス。
- 前記電子部品素子が実装された前記パッケージ基板の上面が、封止樹脂または上蓋により封止されていることを特徴とする、請求項1ないし3のいずれか1項に記載された電子部品デバイス。
- 電子部品素子を実装するためのパッケージ基板において、
前記パッケージ基板が、内部にESD保護素子を備え、
前記ESD保護素子が、少なくとも、前記パッケージ基板の内部に形成された空洞部と、前記空洞部内において対向して形成された一対の放電電極とで構成され、前記パッケージ基板の内部に形成された信号ラインと、前記パッケージ基板の表面に形成されたグランド電極との間に挿入されており、
前記グランド電極が、前記電子部品素子のグランド電極と別個のESD保護素子専用グランド電極であることを特徴とするパッケージ基板。 - 前記ESD保護素子が、さらに、前記空洞部の底部に、金属材料と、前記パッケージ基板を構成する絶縁材料とを含む混合材料からなる混合部を備え、前記一対の放電電極が、前記混合部の上に形成されていることを特徴とする、請求項5に記載されたパッケージ基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011538384A JP5590042B2 (ja) | 2009-11-02 | 2010-10-21 | 電子部品デバイスおよびパッケージ基板 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009251765 | 2009-11-02 | ||
JP2009251765 | 2009-11-02 | ||
JP2011538384A JP5590042B2 (ja) | 2009-11-02 | 2010-10-21 | 電子部品デバイスおよびパッケージ基板 |
PCT/JP2010/068613 WO2011052480A1 (ja) | 2009-11-02 | 2010-10-21 | 電子部品デバイスおよびパッケージ基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2011052480A1 JPWO2011052480A1 (ja) | 2013-03-21 |
JP5590042B2 true JP5590042B2 (ja) | 2014-09-17 |
Family
ID=43921903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011538384A Active JP5590042B2 (ja) | 2009-11-02 | 2010-10-21 | 電子部品デバイスおよびパッケージ基板 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8659861B2 (ja) |
JP (1) | JP5590042B2 (ja) |
KR (1) | KR101385114B1 (ja) |
CN (1) | CN102598260B (ja) |
WO (1) | WO2011052480A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10276517B2 (en) | 2017-03-27 | 2019-04-30 | Toshiba Memory Corporation | Semiconductor device |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015015389A (ja) * | 2013-07-05 | 2015-01-22 | 三菱電機株式会社 | 半導体装置および半導体装置の試験用治具 |
US9853446B2 (en) * | 2015-08-27 | 2017-12-26 | Qualcomm Incorporated | Integrated circuit (IC) package comprising electrostatic discharge (ESD) protection |
TWI661341B (zh) * | 2017-12-22 | 2019-06-01 | 禾瑞亞科技股份有限公司 | 用於與觸控裝置共地之地墊裝置與電子系統 |
CN111010815B (zh) * | 2019-12-27 | 2021-11-09 | 安捷利(番禺)电子实业有限公司 | 一种半导体芯片埋入式线路板及其加工方法、加工装置 |
KR102583344B1 (ko) * | 2020-05-13 | 2023-09-26 | 세메스 주식회사 | 기판 처리 시스템 |
JP2022099532A (ja) | 2020-12-23 | 2022-07-05 | 株式会社村田製作所 | 高周波モジュール及び通信装置 |
CN117240251B (zh) * | 2023-11-16 | 2024-01-30 | 成都频岢微电子有限公司 | 一种模组中滤波器的小型化布局结构 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004146524A (ja) * | 2002-10-23 | 2004-05-20 | Toshiba Corp | 半導体装置 |
WO2008146514A1 (ja) * | 2007-05-28 | 2008-12-04 | Murata Manufacturing Co., Ltd. | Esd保護デバイス |
WO2009136535A1 (ja) * | 2008-05-08 | 2009-11-12 | 株式会社 村田製作所 | Esd保護機能内蔵基板 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US6198136B1 (en) | 1996-03-19 | 2001-03-06 | International Business Machines Corporation | Support chips for buffer circuits |
JP2003123936A (ja) * | 2001-10-16 | 2003-04-25 | Matsushita Electric Ind Co Ltd | 電子部品およびその製造方法 |
US7196406B2 (en) * | 2004-11-22 | 2007-03-27 | Infineon Technologies Ag | ESD protection apparatus for an electrical device |
JP2006294724A (ja) * | 2005-04-07 | 2006-10-26 | Matsushita Electric Ind Co Ltd | 複合電子部品およびその製造方法 |
JP2007265713A (ja) * | 2006-03-28 | 2007-10-11 | Matsushita Electric Ind Co Ltd | 静電気保護材料ペーストおよびそれを用いた静電気対策部品 |
-
2010
- 2010-10-21 CN CN201080049729.8A patent/CN102598260B/zh active Active
- 2010-10-21 KR KR1020127010914A patent/KR101385114B1/ko active IP Right Grant
- 2010-10-21 JP JP2011538384A patent/JP5590042B2/ja active Active
- 2010-10-21 WO PCT/JP2010/068613 patent/WO2011052480A1/ja active Application Filing
-
2012
- 2012-04-13 US US13/446,001 patent/US8659861B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004146524A (ja) * | 2002-10-23 | 2004-05-20 | Toshiba Corp | 半導体装置 |
WO2008146514A1 (ja) * | 2007-05-28 | 2008-12-04 | Murata Manufacturing Co., Ltd. | Esd保護デバイス |
WO2009136535A1 (ja) * | 2008-05-08 | 2009-11-12 | 株式会社 村田製作所 | Esd保護機能内蔵基板 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10276517B2 (en) | 2017-03-27 | 2019-04-30 | Toshiba Memory Corporation | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR20120073305A (ko) | 2012-07-04 |
US8659861B2 (en) | 2014-02-25 |
CN102598260B (zh) | 2015-05-06 |
CN102598260A (zh) | 2012-07-18 |
US20120200965A1 (en) | 2012-08-09 |
WO2011052480A1 (ja) | 2011-05-05 |
KR101385114B1 (ko) | 2014-04-14 |
JPWO2011052480A1 (ja) | 2013-03-21 |
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