JP5581215B2 - 不揮発性ワンタイムプログラマブル及びマルチタイムプログラマブルメモリに組み込まれた集積回路 - Google Patents

不揮発性ワンタイムプログラマブル及びマルチタイムプログラマブルメモリに組み込まれた集積回路 Download PDF

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JP5581215B2
JP5581215B2 JP2010532325A JP2010532325A JP5581215B2 JP 5581215 B2 JP5581215 B2 JP 5581215B2 JP 2010532325 A JP2010532325 A JP 2010532325A JP 2010532325 A JP2010532325 A JP 2010532325A JP 5581215 B2 JP5581215 B2 JP 5581215B2
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drain
region
floating gate
gate
programmable
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JP2011503850A (ja
JP2011503850A5 (enExample
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リウ，デイヴィッド
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インヴェンサス・コーポレイション
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/10—Floating gate memory cells with a single polysilicon layer

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP2010532325A 2007-11-01 2008-11-03 不揮発性ワンタイムプログラマブル及びマルチタイムプログラマブルメモリに組み込まれた集積回路 Expired - Fee Related JP5581215B2 (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US98461507P 2007-11-01 2007-11-01
US60/984,615 2007-11-01
US12/264,076 2008-11-03
PCT/US2008/082294 WO2009059329A1 (en) 2007-11-01 2008-11-03 Integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory
US12/264,060 2008-11-03
US12/264,029 US7782668B2 (en) 2007-11-01 2008-11-03 Integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory
US12/264,029 2008-11-03
US12/264,076 US7787309B2 (en) 2007-11-01 2008-11-03 Method of operating integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory
US12/264,060 US7787304B2 (en) 2007-11-01 2008-11-03 Method of making integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory

Publications (3)

Publication Number Publication Date
JP2011503850A JP2011503850A (ja) 2011-01-27
JP2011503850A5 JP2011503850A5 (enExample) 2012-03-08
JP5581215B2 true JP5581215B2 (ja) 2014-08-27

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US (5) US7782668B2 (enExample)
JP (1) JP5581215B2 (enExample)
WO (1) WO2009059329A1 (enExample)

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Publication number Publication date
US20090116291A1 (en) 2009-05-07
US8300470B2 (en) 2012-10-30
US20100322010A1 (en) 2010-12-23
US20110176365A1 (en) 2011-07-21
JP2011503850A (ja) 2011-01-27
US20090116295A1 (en) 2009-05-07
US7782668B2 (en) 2010-08-24
US20090114972A1 (en) 2009-05-07
US7787304B2 (en) 2010-08-31
US7920426B2 (en) 2011-04-05
WO2009059329A1 (en) 2009-05-07
US7787309B2 (en) 2010-08-31

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