JP5571439B2 - 磁気トンネル接合デバイスおよびこれを製造するための方法 - Google Patents
磁気トンネル接合デバイスおよびこれを製造するための方法 Download PDFInfo
- Publication number
- JP5571439B2 JP5571439B2 JP2010096071A JP2010096071A JP5571439B2 JP 5571439 B2 JP5571439 B2 JP 5571439B2 JP 2010096071 A JP2010096071 A JP 2010096071A JP 2010096071 A JP2010096071 A JP 2010096071A JP 5571439 B2 JP5571439 B2 JP 5571439B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- magnetic layer
- magnetization
- magnetic
- low conductivity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005291 magnetic effect Effects 0.000 title claims description 76
- 238000000034 method Methods 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 125000006850 spacer group Chemical group 0.000 claims description 72
- 239000000463 material Substances 0.000 claims description 56
- 230000005415 magnetization Effects 0.000 claims description 47
- 230000005290 antiferromagnetic effect Effects 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 230000005294 ferromagnetic effect Effects 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 239000003302 ferromagnetic material Substances 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 description 18
- 230000008569 process Effects 0.000 description 12
- 230000000694 effects Effects 0.000 description 9
- 238000013461 design Methods 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 239000002648 laminated material Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000007737 ion beam deposition Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66984—Devices using spin polarized carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/82—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of the magnetic field applied to the device
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
Description
104、404、504、604 シード層
106、406、506、606 反強磁性層
110 トンネル・バリア
112、612 自由層
114 キャップ
116、416 低σバリア層
118 導電ハード・マスク
Claims (20)
- 半導体デバイスを製造するための方法であって、
パターニング配線層の上にシード層を形成するステップと、
前記シード層の上に反強磁性層を形成するステップと、
前記反強磁性層の上に基準層を形成するステップであって、前記反強磁性層が前記基準層をピンする、前記基準層を形成するステップと、
前記基準層の上に絶縁層を形成するステップと、
前記絶縁層の上に自由磁性層を形成するステップと、
前記自由磁性層の上に低伝導率層を形成するステップと、
前記低伝導率層の上にハード・マスクを形成するステップと、
前記ハード・マスクおよび前記低伝導率層の上にスペーサ材料を堆積するステップであって、前記スペーサ材料が高電気伝導率を有し、前記低伝導率層とは異なる電気伝導率を有し、前記スペーサ材料により、前記ハード・マスクの側壁上および前記低伝導率層の側壁上にスペーサが形成される、前記堆積するステップと
を含み、前記基準層が磁気トンネル接合(「MTJ」)積層物の第1の磁性層を形成し、前記自由磁性層が前記MTJ積層物の第2の磁性層を形成し、前記絶縁層が前記第1の磁性層と前記第2の磁性層の絶縁層を形成し、前記第1の磁性層は、前記反強磁性層によって特定の方向にピンされた磁化方向を有し、前記第2の磁性層は、ピンされていない磁化方向を有し、前記第2の磁性層の磁化は、当該第2の磁性層内にスピン偏極電子を注入することによって制御することができる、前記方法。 - 前記第2の磁性層は、前記第1の磁性層の磁化に対して平行に、又は前記第1の磁性層の磁化に対して逆平行に、その磁化を回転させることができる、請求項1に記載の方法。
- 前記平行な磁化は、前記絶縁層に電流を低抵抗で通過させ、又は、
前記逆平行な磁化は、前記絶縁層に電流を高抵抗で通過させる、
請求項2に記載の方法。 - 前記反強磁性層、前記基準層、前記絶縁層及び前記自由磁性層が、前記磁気トンネル接合積層物を形成する、請求項1〜3のいずれか一項に記載の方法。
- 前記ハード・マスクおよび前記低伝導率層を前記自由磁性層までエッチングするステップ
を更に含む、請求項1〜4のいずれか一項に記載の方法。 - 前記自由磁性層の上にキャップ層を堆積するステップであって、前記低伝導率層が前記キャップ層の上に形成される、前記堆積するステップと
を更に含む、請求項1〜5のいずれか一項に記載の方法。 - 前記スペーサ材料を水平方向の表面からエッチングして、前記ハード・マスクおよび前記低伝導率層の側壁のみが前記スペーサ材料を含むようにする、請求項1〜6のいずれか一項に記載の方法。
- 前記スペーサ材料が強磁性材料を含む、請求項1〜7のいずれか一項に記載の方法。
- 前記強磁性スペーサ材料が、前記自由磁性層上の反磁場を変更するように異方性パターニングされる、請求項8に記載の方法。
- 前記スペーサ材料の上に保護スペーサを形成するステップ
を更に含む、請求項1〜9のいずれか一項に記載の方法。 - 半導体デバイスであって、
パターニング配線層を含む基板と、
前記パターニング配線層の上に形成されたシード層と、
前記シード層の上に形成された反強磁性層と、
前記反強磁性層の上に形成された基準層であって、前記反強磁性層が前記基準層をピンする、前記基準層と、
前記基準層の上に形成された絶縁層と、
前記絶縁層の上に形成された自由磁性層と、
前記自由磁性層の上に形成された低伝導率層と、
前記低伝導率層の上に形成されたハード・マスクであって、前記ハード・マスクの材料が高伝導率を有し、前記低伝導率層とは異なる電気伝導率を有する、前記ハード・マスクと、
前記ハード・マスクの側壁上および前記低伝導率層の側壁上に形成されたスペーサであって、前記スペーサの材料が高電気伝導率を有し、前記低伝導率層とは異なる電気伝導率を有する、前記スペーサと
を備えており、
前記基準層が磁気トンネル接合(「MTJ」)積層物の第1の磁性層を形成し、前記自由磁性層が前記MTJ積層物の第2の磁性層を形成し、前記絶縁層が前記第1の磁性層と前記第2の磁性層の絶縁層を形成し、前記第1の磁性層は、前記反強磁性層によって特定の方向にピンされた磁化方向を有し、前記第2の磁性層は、ピンされていない磁化方向を有し、前記第2の磁性層の磁化は、当該第2の磁性層内にスピン偏極電子を注入することによって制御することができる、前記半導体デバイス。 - 前記第2の磁性層は、前記第1の磁性層の磁化に対して平行に、又は前記第1の磁性層の磁化に対して逆平行に、その磁化を回転させることができる、請求項11に記載の半導体デバイス。
- 前記平行な磁化は、前記絶縁層に電流を低抵抗で通過させ、又は、
前記逆平行な磁化は、前記絶縁層に電流を高抵抗で通過させる、
請求項12に記載の半導体デバイス。 - 前記反強磁性層、前記基準層、前記絶縁層及び前記自由磁性層が、前記磁気トンネル接合積層物を形成する、請求項11〜13のいずれか一項に記載の半導体デバイス。
- 前記ハード・マスクおよび前記低伝導率層を前記自由磁性層までエッチングされている、請求項11〜14のいずれか一項に記載の半導体デバイス。
- 前記自由磁性層の上に形成されたキャップ層であって、前記低伝導率層が前記キャップ層の上に形成される、前記キャップ層と
を更に備えている、請求項11〜15のいずれか一項に記載の半導体デバイス。 - 前記ハード・マスクおよび前記低伝導率層の側壁のみが前記スペーサ材料を含む、請求項11〜16のいずれか一項のいずれか一項に記載の半導体デバイス。
- 前記スペーサ材料が強磁性材料である、請求項11〜17のいずれか一項に記載の半導体デバイス。
- 前記強磁性スペーサ材料が、前記自由磁性層上の反磁場を変更するように異方性パターニングされている、請求項18に記載の半導体デバイス。
- 前記スペーサ材料の上に形成された保護スペーサを更に含む、請求項11〜19のいずれか一項に記載の半導体デバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/433,023 US7989224B2 (en) | 2009-04-30 | 2009-04-30 | Sidewall coating for non-uniform spin momentum-transfer magnetic tunnel junction current flow |
US12/433023 | 2009-04-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010263204A JP2010263204A (ja) | 2010-11-18 |
JP5571439B2 true JP5571439B2 (ja) | 2014-08-13 |
Family
ID=43029758
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010096071A Active JP5571439B2 (ja) | 2009-04-30 | 2010-04-19 | 磁気トンネル接合デバイスおよびこれを製造するための方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US7989224B2 (ja) |
JP (1) | JP5571439B2 (ja) |
KR (1) | KR101190377B1 (ja) |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8455117B2 (en) * | 2009-03-04 | 2013-06-04 | Seagate Technology Llc | Bit-patterned stack with antiferromagnetic shell |
US20100327248A1 (en) * | 2009-06-29 | 2010-12-30 | Seagate Technology Llc | Cell patterning with multiple hard masks |
US8492858B2 (en) * | 2009-08-27 | 2013-07-23 | Qualcomm Incorporated | Magnetic tunnel junction device and fabrication |
US8735179B2 (en) * | 2009-08-27 | 2014-05-27 | Qualcomm Incorporated | Magnetic tunnel junction device and fabrication |
JP4929332B2 (ja) * | 2009-09-24 | 2012-05-09 | 株式会社東芝 | 電子部品の製造方法 |
US8513749B2 (en) * | 2010-01-14 | 2013-08-20 | Qualcomm Incorporated | Composite hardmask architecture and method of creating non-uniform current path for spin torque driven magnetic tunnel junction |
US8981502B2 (en) * | 2010-03-29 | 2015-03-17 | Qualcomm Incorporated | Fabricating a magnetic tunnel junction storage element |
US9082695B2 (en) | 2011-06-06 | 2015-07-14 | Avalanche Technology, Inc. | Vialess memory structure and method of manufacturing same |
US8709956B2 (en) | 2011-08-01 | 2014-04-29 | Avalanche Technology Inc. | MRAM with sidewall protection and method of fabrication |
US8796795B2 (en) | 2011-08-01 | 2014-08-05 | Avalanche Technology Inc. | MRAM with sidewall protection and method of fabrication |
KR101870873B1 (ko) * | 2011-08-04 | 2018-07-20 | 에스케이하이닉스 주식회사 | 반도체 소자의 제조방법 |
US8536063B2 (en) | 2011-08-30 | 2013-09-17 | Avalanche Technology Inc. | MRAM etching processes |
US8623735B2 (en) | 2011-09-14 | 2014-01-07 | Globalfoundries Inc. | Methods of forming semiconductor devices having capacitor and via contacts |
KR101617113B1 (ko) * | 2011-12-20 | 2016-04-29 | 인텔 코포레이션 | 자기 메모리 소자 콘택의 크기 감소 및 중심 배치 방법 |
KR101950004B1 (ko) | 2012-03-09 | 2019-02-19 | 삼성전자 주식회사 | 자기 소자 |
US8574928B2 (en) | 2012-04-10 | 2013-11-05 | Avalanche Technology Inc. | MRAM fabrication method with sidewall cleaning |
US8883520B2 (en) | 2012-06-22 | 2014-11-11 | Avalanche Technology, Inc. | Redeposition control in MRAM fabrication process |
US9129690B2 (en) | 2012-07-20 | 2015-09-08 | Samsung Electronics Co., Ltd. | Method and system for providing magnetic junctions having improved characteristics |
US9178009B2 (en) | 2012-10-10 | 2015-11-03 | Globalfoundries Inc. | Methods of forming a capacitor and contact structures |
CN103779413B (zh) * | 2012-10-19 | 2016-09-07 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其制造方法 |
US8901687B2 (en) | 2012-11-27 | 2014-12-02 | Industrial Technology Research Institute | Magnetic device with a substrate, a sensing block and a repair layer |
US8809149B2 (en) | 2012-12-12 | 2014-08-19 | Globalfoundries Inc. | High density serial capacitor device and methods of making such a capacitor device |
KR102034210B1 (ko) | 2013-03-15 | 2019-10-18 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이의 제조 방법, 이 반도체 장치를 포함하는 마이크로프로세서, 프로세서, 시스템, 데이터 저장 시스템 및 메모리 시스템 |
CN104995683B (zh) * | 2013-03-15 | 2018-03-23 | 英特尔公司 | 包括嵌入式磁性隧道结的逻辑芯片 |
JP5865858B2 (ja) * | 2013-03-22 | 2016-02-17 | 株式会社東芝 | 磁気抵抗効果素子及び磁気抵抗効果素子の製造方法 |
US9024399B2 (en) * | 2013-05-02 | 2015-05-05 | Yimin Guo | Perpendicular STT-MRAM having logical magnetic shielding |
US20150019147A1 (en) * | 2013-07-11 | 2015-01-15 | Qualcomm Incorporated | Method and device for estimating damage to magnetic tunnel junction (mtj) elements |
US9595661B2 (en) * | 2013-07-18 | 2017-03-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Magnetoresistive random access memory structure and method of forming the same |
US9070869B2 (en) * | 2013-10-10 | 2015-06-30 | Avalanche Technology, Inc. | Fabrication method for high-density MRAM using thin hard mask |
WO2015147813A1 (en) * | 2014-03-26 | 2015-10-01 | Intel Corporation | Techniques for forming spin-transfer torque memory (sttm) elements having annular contacts |
WO2015147855A1 (en) * | 2014-03-28 | 2015-10-01 | Intel Corporation | Techniques for forming spin-transfer torque memory having a dot-contacted free magnetic layer |
US9269893B2 (en) | 2014-04-02 | 2016-02-23 | Qualcomm Incorporated | Replacement conductive hard mask for multi-step magnetic tunnel junction (MTJ) etch |
US9349939B2 (en) * | 2014-05-23 | 2016-05-24 | Qualcomm Incorporated | Etch-resistant protective coating for a magnetic tunnel junction device |
US10003014B2 (en) * | 2014-06-20 | 2018-06-19 | International Business Machines Corporation | Method of forming an on-pitch self-aligned hard mask for contact to a tunnel junction using ion beam etching |
US9362336B2 (en) * | 2014-09-11 | 2016-06-07 | Qualcomm Incorporated | Sub-lithographic patterning of magnetic tunneling junction devices |
KR102214507B1 (ko) | 2014-09-15 | 2021-02-09 | 삼성전자 주식회사 | 자기 메모리 장치 |
JP6498968B2 (ja) | 2015-03-11 | 2019-04-10 | 株式会社東芝 | 磁気抵抗素子および磁気メモリ |
US20170069832A1 (en) * | 2015-09-03 | 2017-03-09 | Yong-Jae Kim | Magnetoresistive memory devices and methods of manufacturing the same |
KR102465539B1 (ko) | 2015-09-18 | 2022-11-11 | 삼성전자주식회사 | 자기 터널 접합 구조체를 포함하는 반도체 소자 및 그의 형성 방법 |
KR102473663B1 (ko) | 2015-10-01 | 2022-12-02 | 삼성전자주식회사 | 자기 터널 접합 구조체를 포함하는 반도체 소자 및 그의 형성 방법 |
US9905751B2 (en) * | 2015-10-20 | 2018-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Magnetic tunnel junction with reduced damage |
JP2017126613A (ja) * | 2016-01-12 | 2017-07-20 | 株式会社東芝 | 磁気抵抗効果素子及びその製造方法 |
US11037611B2 (en) | 2018-03-23 | 2021-06-15 | Samsung Electronics Co., Ltd. | Magnetic property measuring systems, methods for measuring magnetic properties, and methods for manufacturing magnetic memory devices using the same |
US10923652B2 (en) * | 2019-06-21 | 2021-02-16 | Applied Materials, Inc. | Top buffer layer for magnetic tunnel junction application |
CN110828558B (zh) * | 2019-10-29 | 2021-07-30 | 北京航空航天大学 | 一种自旋电子器件制备方法、制备工件及其制备方法 |
CN112750943A (zh) * | 2019-10-30 | 2021-05-04 | 上海磁宇信息科技有限公司 | 磁性隧道结结构及制作方法 |
US11223008B2 (en) * | 2019-11-27 | 2022-01-11 | International Business Machines Corporation | Pillar-based memory hardmask smoothing and stress reduction |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005527101A (ja) * | 2001-08-21 | 2005-09-08 | シーゲイト テクノロジー エルエルシー | 炭素ベースのガスを用いる磁気薄膜のイオンビームエッチング選択性の向上 |
JP2004259913A (ja) * | 2003-02-26 | 2004-09-16 | Sony Corp | 環状体の製造方法および磁気記憶装置およびその製造方法 |
US6911156B2 (en) | 2003-04-16 | 2005-06-28 | Freescale Semiconductor, Inc. | Methods for fabricating MRAM device structures |
US6927075B2 (en) * | 2003-08-25 | 2005-08-09 | Headway Technologies, Inc. | Magnetic memory with self-aligned magnetic keeper structure |
US7374952B2 (en) | 2004-06-17 | 2008-05-20 | Infineon Technologies Ag | Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof |
US7241632B2 (en) | 2005-04-14 | 2007-07-10 | Headway Technologies, Inc. | MTJ read head with sidewall spacers |
US7399646B2 (en) | 2005-08-23 | 2008-07-15 | International Business Machines Corporation | Magnetic devices and techniques for formation thereof |
US7531367B2 (en) | 2006-01-18 | 2009-05-12 | International Business Machines Corporation | Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit |
JP2008130807A (ja) * | 2006-11-21 | 2008-06-05 | Toshiba Corp | 磁気ランダムアクセスメモリ及びその製造方法 |
JP2008159613A (ja) * | 2006-12-20 | 2008-07-10 | Toshiba Corp | 磁気ランダムアクセスメモリ及びその書き込み方法 |
US8133745B2 (en) * | 2007-10-17 | 2012-03-13 | Magic Technologies, Inc. | Method of magnetic tunneling layer processes for spin-transfer torque MRAM |
-
2009
- 2009-04-30 US US12/433,023 patent/US7989224B2/en active Active
-
2010
- 2010-03-23 KR KR1020100025813A patent/KR101190377B1/ko active IP Right Grant
- 2010-04-19 JP JP2010096071A patent/JP5571439B2/ja active Active
-
2011
- 2011-05-03 US US13/100,123 patent/US8338869B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20110204459A1 (en) | 2011-08-25 |
KR20100119493A (ko) | 2010-11-09 |
JP2010263204A (ja) | 2010-11-18 |
KR101190377B1 (ko) | 2012-10-11 |
US20100276768A1 (en) | 2010-11-04 |
US8338869B2 (en) | 2012-12-25 |
US7989224B2 (en) | 2011-08-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5571439B2 (ja) | 磁気トンネル接合デバイスおよびこれを製造するための方法 | |
US8697454B2 (en) | Methods of forming spin torque devices and structures formed thereby | |
CN106505146B (zh) | 磁穿隧接面及三维磁穿隧接面数组 | |
US6781173B2 (en) | MRAM sense layer area control | |
KR102499931B1 (ko) | 반도체 mram 디바이스 및 방법 | |
US8796041B2 (en) | Pillar-based interconnects for magnetoresistive random access memory | |
US9281168B2 (en) | Reducing switching variation in magnetoresistive devices | |
JP2005150739A (ja) | 薄膜デバイスおよび該薄膜デバイスにおいて熱による補助を実施する方法 | |
US9917247B2 (en) | Structure for thermally assisted MRAM | |
TWI409813B (zh) | 與多元件自由層磁穿隧接合之調整插接層及形成其之方法 | |
US11895928B2 (en) | Integration scheme for three terminal spin-orbit-torque (SOT) switching devices | |
US9023219B2 (en) | Method of manufacturing a magnetoresistive device | |
US20190288191A1 (en) | Selective growth of seed layer for magneto-resistive random access memory | |
US9799823B1 (en) | High temperature endurable MTJ stack | |
US10868236B2 (en) | Method for manufacturing reduced pitch magnetic random access memory pillar | |
JP2004047992A (ja) | データ層内に制御された核形成場所を有する磁気メモリ素子 | |
JP2021507543A (ja) | Nvmクラスとsramクラスのmram素子をそのチップ上で組み合わせる方法 | |
US10811594B2 (en) | Process for hard mask development for MRAM pillar formation using photolithography | |
CN112349830A (zh) | 磁存储器件 | |
CN104037321B (zh) | 伸长的磁阻式隧道结结构 | |
US20230397501A1 (en) | Memory device and formation method thereof | |
US10411185B1 (en) | Process for creating a high density magnetic tunnel junction array test platform | |
US20190207101A1 (en) | Photolithographic method for fabricating dense pillar arrays using spacers as a pattern |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130115 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140212 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140303 Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140303 |
|
RD12 | Notification of acceptance of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7432 Effective date: 20140303 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140306 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140509 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140512 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140512 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140610 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140610 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20140610 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140626 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5571439 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |