JP5547878B2 - 半導体加工方法 - Google Patents

半導体加工方法 Download PDF

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Publication number
JP5547878B2
JP5547878B2 JP2008170629A JP2008170629A JP5547878B2 JP 5547878 B2 JP5547878 B2 JP 5547878B2 JP 2008170629 A JP2008170629 A JP 2008170629A JP 2008170629 A JP2008170629 A JP 2008170629A JP 5547878 B2 JP5547878 B2 JP 5547878B2
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JP
Japan
Prior art keywords
gas
film
plasma
resist
processing method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008170629A
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English (en)
Japanese (ja)
Other versions
JP2010010573A (ja
JP2010010573A5 (https=
Inventor
哲郎 小野
剛 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi High Tech Corp
Original Assignee
Hitachi High Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi High Technologies Corp filed Critical Hitachi High Technologies Corp
Priority to JP2008170629A priority Critical patent/JP5547878B2/ja
Priority to TW097129876A priority patent/TWI485771B/zh
Priority to KR1020080080484A priority patent/KR100981041B1/ko
Priority to US12/198,222 priority patent/US8440513B2/en
Publication of JP2010010573A publication Critical patent/JP2010010573A/ja
Publication of JP2010010573A5 publication Critical patent/JP2010010573A5/ja
Application granted granted Critical
Publication of JP5547878B2 publication Critical patent/JP5547878B2/ja
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/273—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a delineation of conductive layers, e.g. by RIE
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/669—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Landscapes

  • Drying Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
JP2008170629A 2008-06-30 2008-06-30 半導体加工方法 Expired - Fee Related JP5547878B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2008170629A JP5547878B2 (ja) 2008-06-30 2008-06-30 半導体加工方法
TW097129876A TWI485771B (zh) 2008-06-30 2008-08-06 Semiconductor processing methods
KR1020080080484A KR100981041B1 (ko) 2008-06-30 2008-08-18 반도체 가공방법
US12/198,222 US8440513B2 (en) 2008-06-30 2008-08-26 Method of semiconductor processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008170629A JP5547878B2 (ja) 2008-06-30 2008-06-30 半導体加工方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2014081175A Division JP2014131086A (ja) 2014-04-10 2014-04-10 プラズマ処理方法

Publications (3)

Publication Number Publication Date
JP2010010573A JP2010010573A (ja) 2010-01-14
JP2010010573A5 JP2010010573A5 (https=) 2013-04-04
JP5547878B2 true JP5547878B2 (ja) 2014-07-16

Family

ID=41447974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008170629A Expired - Fee Related JP5547878B2 (ja) 2008-06-30 2008-06-30 半導体加工方法

Country Status (4)

Country Link
US (1) US8440513B2 (https=)
JP (1) JP5547878B2 (https=)
KR (1) KR100981041B1 (https=)
TW (1) TWI485771B (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5250476B2 (ja) * 2009-05-11 2013-07-31 株式会社日立ハイテクノロジーズ ドライエッチング方法
US9318345B2 (en) * 2011-10-05 2016-04-19 Globalfoundries Inc. Enhancing transistor performance by reducing exposure to oxygen plasma in a dual stress liner approach
JP6002411B2 (ja) * 2012-03-28 2016-10-05 芝浦メカトロニクス株式会社 Ｅｕｖマスク製造方法およびｅｕｖマスク製造装置
US8853081B2 (en) * 2012-12-27 2014-10-07 Intermolecular, Inc. High dose ion-implanted photoresist removal using organic solvent and transition metal mixtures
JP2014212310A (ja) * 2013-04-02 2014-11-13 東京エレクトロン株式会社 半導体デバイスの製造方法及び製造装置
JP7033912B2 (ja) * 2017-12-22 2022-03-11 株式会社Ｓｃｒｅｅｎホールディングス 基板処理装置及び基板処理方法
WO2025182676A1 (ja) * 2024-03-01 2025-09-04 東京エレクトロン株式会社 ナノピラーの形成方法及びドライエッチング装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3563446B2 (ja) * 1993-07-16 2004-09-08 富士通株式会社 半導体装置の製造方法
JPH1168095A (ja) * 1997-08-11 1999-03-09 Fujitsu Ltd 半導体装置の製造方法
US5962346A (en) * 1997-12-29 1999-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fluorine-doped silicate glass hard mask to improve metal line etching profile
US6281135B1 (en) * 1999-08-05 2001-08-28 Axcelis Technologies, Inc. Oxygen free plasma stripping process
US6593244B1 (en) * 2000-09-11 2003-07-15 Applied Materials Inc. Process for etching conductors at high etch rates
JP4142664B2 (ja) * 2001-03-12 2008-09-03 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6951823B2 (en) * 2001-05-14 2005-10-04 Axcelis Technologies, Inc. Plasma ashing process
US6762130B2 (en) * 2002-05-31 2004-07-13 Texas Instruments Incorporated Method of photolithographically forming extremely narrow transistor gate elements
US20050020856A1 (en) * 2003-07-24 2005-01-27 The Regents Of The University Of Califorinia Process for production of acetyl anhydrides and optionally acetic acid from methane and carbon dioxide
US7799685B2 (en) * 2003-10-13 2010-09-21 Mattson Technology, Inc. System and method for removal of photoresist in transistor fabrication for integrated circuit manufacturing
JP2005268312A (ja) * 2004-03-16 2005-09-29 Semiconductor Leading Edge Technologies Inc レジスト除去方法及びそれを用いて製造した半導体装置
US7449416B2 (en) * 2004-09-01 2008-11-11 Axcelis Technologies, Inc. Apparatus and plasma ashing process for increasing photoresist removal rate
US7319074B2 (en) * 2005-06-13 2008-01-15 United Microelectronics Corp. Method of defining polysilicon patterns
US20070037101A1 (en) * 2005-08-15 2007-02-15 Fujitsu Limited Manufacture method for micro structure
JP4854245B2 (ja) * 2005-09-22 2012-01-18 東京エレクトロン株式会社 半導体装置の製造方法
US7642195B2 (en) * 2005-09-26 2010-01-05 Applied Materials, Inc. Hydrogen treatment to improve photoresist adhesion and rework consistency
JP4598639B2 (ja) * 2005-09-27 2010-12-15 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
KR100827435B1 (ko) * 2006-01-31 2008-05-06 삼성전자주식회사 반도체 소자에서 무산소 애싱 공정을 적용한 게이트 형성방법
US7381651B2 (en) * 2006-03-22 2008-06-03 Axcelis Technologies, Inc. Processes for monitoring the levels of oxygen and/or nitrogen species in a substantially oxygen and nitrogen-free plasma ashing process
US7691754B2 (en) * 2006-10-18 2010-04-06 United Microelectronics Corp. Method for removing photoresist layer and method of forming opening
US7704888B2 (en) * 2007-01-23 2010-04-27 Globalfoundries Inc. Methods for removing photoresist from semiconductor structures having high-k dielectric material layers

Also Published As

Publication number Publication date
US20090325388A1 (en) 2009-12-31
US8440513B2 (en) 2013-05-14
JP2010010573A (ja) 2010-01-14
KR20100003148A (ko) 2010-01-07
TW201001535A (en) 2010-01-01
KR100981041B1 (ko) 2010-09-08
TWI485771B (zh) 2015-05-21

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