JP5546194B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5546194B2
JP5546194B2 JP2009229508A JP2009229508A JP5546194B2 JP 5546194 B2 JP5546194 B2 JP 5546194B2 JP 2009229508 A JP2009229508 A JP 2009229508A JP 2009229508 A JP2009229508 A JP 2009229508A JP 5546194 B2 JP5546194 B2 JP 5546194B2
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JP
Japan
Prior art keywords
etching
gan
semiconductor layer
semiconductor device
sic substrate
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Active
Application number
JP2009229508A
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English (en)
Japanese (ja)
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JP2011077434A5 (https=
JP2011077434A (ja
Inventor
俊行 河阪
春雄 川田
務 駒谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Device Innovations Inc
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Sumitomo Electric Device Innovations Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Device Innovations Inc filed Critical Sumitomo Electric Device Innovations Inc
Priority to JP2009229508A priority Critical patent/JP5546194B2/ja
Priority to US12/893,481 priority patent/US8476166B2/en
Publication of JP2011077434A publication Critical patent/JP2011077434A/ja
Publication of JP2011077434A5 publication Critical patent/JP2011077434A5/ja
Application granted granted Critical
Publication of JP5546194B2 publication Critical patent/JP5546194B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
JP2009229508A 2009-10-01 2009-10-01 半導体装置の製造方法 Active JP5546194B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009229508A JP5546194B2 (ja) 2009-10-01 2009-10-01 半導体装置の製造方法
US12/893,481 US8476166B2 (en) 2009-10-01 2010-09-29 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009229508A JP5546194B2 (ja) 2009-10-01 2009-10-01 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2011077434A JP2011077434A (ja) 2011-04-14
JP2011077434A5 JP2011077434A5 (https=) 2012-10-18
JP5546194B2 true JP5546194B2 (ja) 2014-07-09

Family

ID=43823503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009229508A Active JP5546194B2 (ja) 2009-10-01 2009-10-01 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US8476166B2 (https=)
JP (1) JP5546194B2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5566803B2 (ja) * 2010-07-21 2014-08-06 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
US8993437B2 (en) * 2011-10-27 2015-03-31 Infineon Technologies Ag Method for etching substrate
CN103531527B (zh) * 2012-07-03 2016-07-06 中芯国际集成电路制造(上海)有限公司 金属互连结构的制作方法
CN102903671A (zh) * 2012-10-12 2013-01-30 江阴长电先进封装有限公司 一种新型的芯片背面硅通孔结构的成形方法
US20150099358A1 (en) * 2013-10-07 2015-04-09 Win Semiconductors Corp. Method for forming through wafer vias in semiconductor devices
CN104599949A (zh) * 2014-12-30 2015-05-06 上海师范大学 基于SiC衬底片深刻蚀光滑表面的加工工艺
JP6863574B2 (ja) * 2017-02-22 2021-04-21 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
JP2019145546A (ja) 2018-02-16 2019-08-29 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
JP7070848B2 (ja) * 2018-07-26 2022-05-18 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008098456A (ja) * 2006-10-13 2008-04-24 Eudyna Devices Inc 半導体装置の製造方法
JP5298559B2 (ja) * 2007-06-29 2013-09-25 富士通株式会社 半導体装置及びその製造方法
US8003525B2 (en) * 2007-06-29 2011-08-23 Fujitsu Limited Semiconductor device and method of manufacturing the same
JP5262185B2 (ja) * 2008-02-29 2013-08-14 富士通株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
US20110081784A1 (en) 2011-04-07
JP2011077434A (ja) 2011-04-14
US8476166B2 (en) 2013-07-02

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