JP5514559B2 - 配線基板及びその製造方法並びに半導体パッケージ - Google Patents

配線基板及びその製造方法並びに半導体パッケージ Download PDF

Info

Publication number
JP5514559B2
JP5514559B2 JP2010004394A JP2010004394A JP5514559B2 JP 5514559 B2 JP5514559 B2 JP 5514559B2 JP 2010004394 A JP2010004394 A JP 2010004394A JP 2010004394 A JP2010004394 A JP 2010004394A JP 5514559 B2 JP5514559 B2 JP 5514559B2
Authority
JP
Japan
Prior art keywords
substrate
layer
wiring
ceramic
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010004394A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011146445A5 (enExample
JP2011146445A (ja
Inventor
直 荒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010004394A priority Critical patent/JP5514559B2/ja
Priority to US12/987,398 priority patent/US8686548B2/en
Publication of JP2011146445A publication Critical patent/JP2011146445A/ja
Publication of JP2011146445A5 publication Critical patent/JP2011146445A5/ja
Application granted granted Critical
Publication of JP5514559B2 publication Critical patent/JP5514559B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2010004394A 2010-01-12 2010-01-12 配線基板及びその製造方法並びに半導体パッケージ Active JP5514559B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010004394A JP5514559B2 (ja) 2010-01-12 2010-01-12 配線基板及びその製造方法並びに半導体パッケージ
US12/987,398 US8686548B2 (en) 2010-01-12 2011-01-10 Wiring substrate, method for manufacturing wiring substrate, and semiconductor package including wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010004394A JP5514559B2 (ja) 2010-01-12 2010-01-12 配線基板及びその製造方法並びに半導体パッケージ

Publications (3)

Publication Number Publication Date
JP2011146445A JP2011146445A (ja) 2011-07-28
JP2011146445A5 JP2011146445A5 (enExample) 2013-02-21
JP5514559B2 true JP5514559B2 (ja) 2014-06-04

Family

ID=44257896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010004394A Active JP5514559B2 (ja) 2010-01-12 2010-01-12 配線基板及びその製造方法並びに半導体パッケージ

Country Status (2)

Country Link
US (1) US8686548B2 (enExample)
JP (1) JP5514559B2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8501587B2 (en) * 2009-01-13 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated chips and methods of fabrication thereof
US8780576B2 (en) * 2011-09-14 2014-07-15 Invensas Corporation Low CTE interposer
US8912045B2 (en) * 2012-06-12 2014-12-16 International Business Machines Corporation Three dimensional flip chip system and method
US8927345B2 (en) * 2012-07-09 2015-01-06 Freescale Semiconductor, Inc. Device package with rigid interconnect structure connecting die and substrate and method thereof
US9583426B2 (en) 2014-11-05 2017-02-28 Invensas Corporation Multi-layer substrates suitable for interconnection between circuit modules
US9633930B2 (en) * 2014-11-26 2017-04-25 Kookmin University Industry Academy Cooperation Foundation Method of forming through-hole in silicon substrate, method of forming electrical connection element penetrating silicon substrate and semiconductor device manufactured thereby
US9969614B2 (en) 2015-05-29 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS packages and methods of manufacture thereof
US10283492B2 (en) 2015-06-23 2019-05-07 Invensas Corporation Laminated interposers and packages with embedded trace interconnects
KR102439483B1 (ko) * 2015-10-08 2022-09-02 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US9852994B2 (en) 2015-12-14 2017-12-26 Invensas Corporation Embedded vialess bridges
US9953911B2 (en) * 2016-07-01 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and method
TWI800487B (zh) * 2016-09-09 2023-05-01 日商索尼半導體解決方案公司 固體攝像元件及製造方法、以及電子機器
CN115547846A (zh) * 2019-02-21 2022-12-30 奥特斯科技(重庆)有限公司 部件承载件及其制造方法和电气装置
US12205877B2 (en) 2019-02-21 2025-01-21 AT&S(Chongqing) Company Limited Ultra-thin component carrier having high stiffness and method of manufacturing the same
IT201900006736A1 (it) * 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100337658B1 (ko) * 1997-04-03 2002-05-24 사토 요시하루 회로 기판 및 검출기 그리고 이의 제조 방법
US6617681B1 (en) 1999-06-28 2003-09-09 Intel Corporation Interposer and method of making same
DE10010461A1 (de) * 2000-03-03 2001-09-13 Infineon Technologies Ag Vorrichtung zum Verpacken elektronischer Bauteile mittels Spritzgußtechnik
JP2002299486A (ja) 2001-03-29 2002-10-11 Kyocera Corp 光半導体素子収納用パッケージ
US6791133B2 (en) 2002-07-19 2004-09-14 International Business Machines Corporation Interposer capacitor built on silicon wafer and joined to a ceramic substrate
JP4295682B2 (ja) 2004-06-28 2009-07-15 Ｔｄｋ株式会社 多層配線基板
US7221050B2 (en) * 2004-09-02 2007-05-22 Intel Corporation Substrate having a functionally gradient coefficient of thermal expansion
JP2007123371A (ja) 2005-10-26 2007-05-17 Kyocera Corp 多数個取り電子装置およびその製造方法
JP4738228B2 (ja) 2006-03-28 2011-08-03 富士通株式会社 半導体装置及び半導体装置の製造方法
JP2008160019A (ja) 2006-12-26 2008-07-10 Shinko Electric Ind Co Ltd 電子部品
US20080284037A1 (en) * 2007-05-15 2008-11-20 Andry Paul S Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers
US8455766B2 (en) * 2007-08-08 2013-06-04 Ibiden Co., Ltd. Substrate with low-elasticity layer and low-thermal-expansion layer
US7936060B2 (en) * 2009-04-29 2011-05-03 International Business Machines Corporation Reworkable electronic device assembly and method

Also Published As

Publication number Publication date
JP2011146445A (ja) 2011-07-28
US20110169133A1 (en) 2011-07-14
US8686548B2 (en) 2014-04-01

Similar Documents

Publication Publication Date Title
JP5514559B2 (ja) 配線基板及びその製造方法並びに半導体パッケージ
JP5590869B2 (ja) 配線基板及びその製造方法並びに半導体パッケージ
JP4343044B2 (ja) インターポーザ及びその製造方法並びに半導体装置
KR100621438B1 (ko) 감광성 폴리머를 이용한 적층 칩 패키지 및 그의 제조 방법
KR100595889B1 (ko) 상하도전층의 도통부를 갖는 반도체장치 및 그 제조방법
US8209856B2 (en) Printed wiring board and method for manufacturing the same
JP5005603B2 (ja) 半導体装置及びその製造方法
JP4251421B2 (ja) 半導体装置の製造方法
JP4701506B2 (ja) 回路ブロック体の製造方法、配線回路装置の製造方法並びに半導体装置の製造方法
US20100025081A1 (en) Wiring substrate and electronic component device
JP5636265B2 (ja) 半導体パッケージ及びその製造方法
JP5138395B2 (ja) 配線基板及びその製造方法
US20090135574A1 (en) Wiring board, semiconductor device having wiring board, and method of manufacturing wiring board
US9935053B2 (en) Electronic component integrated substrate
JP5942823B2 (ja) 電子部品装置の製造方法、電子部品装置及び電子装置
JP2011096903A (ja) 半導体素子実装配線基板の製造方法
JP2011155149A (ja) 配線基板及びその製造方法並びに半導体パッケージ
JP4157829B2 (ja) 半導体装置およびその製造方法
JP5877673B2 (ja) 配線基板及びその製造方法、半導体パッケージ
JP2010118589A (ja) 電子部品内蔵配線基板の製造方法
JP4268560B2 (ja) 電子部品内蔵モジュールおよびその製造方法
JP5734624B2 (ja) 半導体パッケージの製造方法
JP2005150344A (ja) 半導体装置およびその製造方法
JP2013098373A (ja) 半導体装置及び半導体装置の製造方法
JP5067056B2 (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121227

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20121227

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130920

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20131210

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140131

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140325

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140331

R150 Certificate of patent or registration of utility model

Ref document number: 5514559

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150