JP5503995B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP5503995B2
JP5503995B2 JP2010027443A JP2010027443A JP5503995B2 JP 5503995 B2 JP5503995 B2 JP 5503995B2 JP 2010027443 A JP2010027443 A JP 2010027443A JP 2010027443 A JP2010027443 A JP 2010027443A JP 5503995 B2 JP5503995 B2 JP 5503995B2
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etching
region
electrode layer
film
resist mask
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Expired - Fee Related
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JP2010027443A
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English (en)
Japanese (ja)
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JP2010212670A5 (enExample
JP2010212670A (ja
Inventor
秀和 宮入
佑太 遠藤
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2010027443A priority Critical patent/JP5503995B2/ja
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Publication of JP2010212670A5 publication Critical patent/JP2010212670A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
JP2010027443A 2009-02-13 2010-02-10 半導体装置の作製方法 Expired - Fee Related JP5503995B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010027443A JP5503995B2 (ja) 2009-02-13 2010-02-10 半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2009030647 2009-02-13
JP2009030647 2009-02-13
JP2010027443A JP5503995B2 (ja) 2009-02-13 2010-02-10 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2010212670A JP2010212670A (ja) 2010-09-24
JP2010212670A5 JP2010212670A5 (enExample) 2013-01-17
JP5503995B2 true JP5503995B2 (ja) 2014-05-28

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US (1) US8143170B2 (enExample)
JP (1) JP5503995B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7989234B2 (en) 2009-02-16 2011-08-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing thin film transistor and method for manufacturing display device
JP5539765B2 (ja) * 2009-03-26 2014-07-02 株式会社半導体エネルギー研究所 トランジスタの作製方法
CN102881571B (zh) * 2012-09-28 2014-11-26 京东方科技集团股份有限公司 有源层离子注入方法及薄膜晶体管有源层离子注入方法
CN104538307B (zh) * 2014-12-19 2018-07-06 深圳市华星光电技术有限公司 一种用于制作多晶硅薄膜晶体管的方法
DE102019119289B4 (de) * 2018-08-24 2023-11-30 Infineon Technologies Ag Träger, laminat und verfahren zum herstellen von halbleitervorrichtungen
US10727216B1 (en) 2019-05-10 2020-07-28 Sandisk Technologies Llc Method for removing a bulk substrate from a bonded assembly of wafers
EP3845976B1 (fr) * 2019-12-30 2024-03-20 The Swatch Group Research and Development Ltd Cadran de montre ayant un affichage à base de diodes électroluminescentes organiques

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US6493048B1 (en) 1998-10-21 2002-12-10 Samsung Electronics Co., Ltd. Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same
KR100325079B1 (ko) 1999-12-22 2002-03-02 주식회사 현대 디스플레이 테크놀로지 고개구율 및 고투과율 액정표시장치의 제조방법
KR100494683B1 (ko) 2000-05-31 2005-06-13 비오이 하이디스 테크놀로지 주식회사 4-마스크를 이용한 박막 트랜지스터 액정표시장치의제조시에 사용하는 할프톤 노광 공정용 포토 마스크
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JP5380037B2 (ja) 2007-10-23 2014-01-08 株式会社半導体エネルギー研究所 半導体装置の作製方法
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JP5427390B2 (ja) 2007-10-23 2014-02-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR101448903B1 (ko) 2007-10-23 2014-10-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치 및 그의 제작방법
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JP2010212670A (ja) 2010-09-24
US20100210078A1 (en) 2010-08-19
US8143170B2 (en) 2012-03-27

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