JP5805973B2 - 半導体基板の作製方法 - Google Patents
半導体基板の作製方法 Download PDFInfo
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- JP5805973B2 JP5805973B2 JP2011074507A JP2011074507A JP5805973B2 JP 5805973 B2 JP5805973 B2 JP 5805973B2 JP 2011074507 A JP2011074507 A JP 2011074507A JP 2011074507 A JP2011074507 A JP 2011074507A JP 5805973 B2 JP5805973 B2 JP 5805973B2
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- crystal semiconductor
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description
本実施の形態では、半導体基板の作製おいて、高機能な半導体集積回路を形成する半導体基板としての実用に耐えうる、平坦性の高い劈開面を有する単結晶半導体層を備えた半導体基板の作製方法について説明する。
本実施の形態では、実施の形態1において、単結晶半導体基板よりベース基板へ単結晶半導体層を接合する工程の異なる例を示す。従って、実施の形態1と同一部分又は同様な機能を有する部分の繰り返しの説明は省略する。
本実施の形態では、薄型で高性能な半導体素子を有する半導体集積回路を実装し、歩留まりよく作製することを目的とした半導体装置の作製方法の一例としてCMOS(相補型金属酸化物半導体:Complementary Metal Oxide Semiconductor)に関して図4及び図5を用いて説明する。なお、実施の形態1と同一部分又は同様な機能を有する部分の繰り返しの説明は省略する。
実施の形態3で作製された半導体装置を適用することで、様々な電子機器に本発明を実施できる。
102 絶縁層
103 希ガスイオン照射
104 第一の損傷領域
105 レーザー光
106 第二の損傷領域
107 水素イオン照射
108 脆化領域
109 レーザー光
110 単結晶半導体層
200 ベース基板
1205 単結晶半導体層
1206 単結晶半導体層
1207 ゲート絶縁層
1208 ゲート電極層
1209 ゲート電極層
1210 n型を付与する不純物元素
1211 マスク
1212a 第一のn型不純物領域
1212b 第一のn型不純物領域
1213 p型を付与する不純物元素
1214 マスク
1215a 第一のp型不純物領域
1215b 第一のp型不純物領域
1216a 側壁絶縁層
1216b 側壁絶縁層
1216c 側壁絶縁層
1216d 側壁絶縁層
1217 n型を付与する不純物元素
1218 マスク
1219a 第二のn型不純物領域
1219b 第二のn型不純物領域
1220a 第三のn型不純物領域
1220b 第三のn型不純物領域
1221 チャネル形成領域
1222 p型を付与する不純物元素
1223 マスク
1224a 第二のp型不純物領域
1224b 第二のp型不純物領域
1225a 第三のp型不純物領域
1225b 第三のp型不純物領域
1226 チャネル形成領域
1227 絶縁膜
1228 絶縁層
1229a 配線層
1229b 配線層
1230a 配線層
1230b 配線層
1231 トランジスタ
1232 トランジスタ
1233a ゲート絶縁層
1233b ゲート絶縁層
9101 本体
9102 表示部
9201 本体
9202 表示部
9301 本体
9302 表示部
9401 本体
9402 表示部
9701 表示部
9702 表示部
Claims (3)
- 単結晶半導体基板の一面に対して希ガスイオンを照射して前記単結晶半導体基板内に第一の損傷領域を形成し、
前記単結晶半導体基板の一面に対してレーザー光を照射して、前記第一の損傷領域の前記一面に近い一部を溶融させて結晶欠陥を回復させ、残部を第二の損傷領域として形成し、
前記単結晶半導体基板の一面に対して前記第二の損傷領域に水素イオンを照射して前記単結晶半導体基板の一面から一定の深さに脆化領域を形成し、
前記単結晶半導体基板とベース基板とを、重ね合わせた状態で、前記脆化領域を劈開面として、前記単結晶半導体基板を前記脆化領域で分離する熱処理を行い、
前記単結晶半導体基板から単結晶半導体層を前記ベース基板上に形成することを特徴とする半導体基板の作製方法。 - 単結晶半導体基板の一面に対して希ガスイオンを照射して前記単結晶半導体基板内に第一の損傷領域を形成し、
前記単結晶半導体基板の一面に対してレーザー光を照射して、前記第一の損傷領域の前記一面に近い一部を溶融させて結晶欠陥を回復させ、残部を第二の損傷領域として形成し、
前記単結晶半導体基板の一面に対して前記第二の損傷領域に水素イオンを照射して前記単結晶半導体基板の一面から一定の深さに脆化領域を形成し、
前記単結晶半導体基板の一面に対して第二のレーザー光を照射して前記単結晶半導体基板の一面と前記脆化領域間の領域を溶融し、
前記単結晶半導体基板とベース基板とを、重ね合わせた状態で、前記脆化領域を劈開面として、前記単結晶半導体基板を前記脆化領域で分離する熱処理を行い、
前記単結晶半導体基板から単結晶半導体層を前記ベース基板上に形成することを特徴とする半導体基板の作製方法。 - 請求項1または請求項2において、
前記希ガスイオンはヘリウムイオンであることを特徴とする半導体基板の作製方法。
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