JP2011228650A - 半導体基板の作製方法及び半導体装置の作製方法 - Google Patents
半導体基板の作製方法及び半導体装置の作製方法 Download PDFInfo
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- JP2011228650A JP2011228650A JP2011065142A JP2011065142A JP2011228650A JP 2011228650 A JP2011228650 A JP 2011228650A JP 2011065142 A JP2011065142 A JP 2011065142A JP 2011065142 A JP2011065142 A JP 2011065142A JP 2011228650 A JP2011228650 A JP 2011228650A
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Classifications
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
【解決手段】半導体基板の作製工程において、単結晶半導体基板に脆化領域を形成する際、単結晶半導体基板表面に対して複数の(少なくとも二つ以上の)異なる角度で斜め方向から水素イオンを照射することによって、単結晶半導体基板に付着する異物の影響を低減し、均一な単結晶半導体層を有する半導体基板を歩留まりよく作製することができる。
【選択図】図1
Description
図1を用いて、半導体層が設けられた基板の作製方法の一例について説明する。具体的には、絶縁層を介して単結晶半導体層が設けられた基板の作製方法(半導体基板の作製方法)について説明する。
実施の形態1において、単結晶半導体基板へ2回目の水素イオン照射をする際、異物除去工程を行う例を示す。従って、実施の形態1と同一部分又は同様な機能を有する部分の繰り返しの説明は省略する。
実施の形態1において、単結晶半導体基板へ水素イオン照射をする工程が異なる例を示す。従って、実施の形態1と同一部分又は同様な機能を有する部分の繰り返しの説明は省略する。
本実施の形態では、薄型で高性能な半導体素子を有する半導体集積回路を実装し、歩留まりよく作製することを目的とした半導体装置の作製方法の一例としてCMOS(相補型金属酸化物半導体:Complementary Metal Oxide Semiconductor)構造の作製方法に関して図7及び図8を用いて説明する。なお、他の実施の形態と同一部分又は同様な機能を有する部分の繰り返しの説明は省略する。
実施の形態4で作製された半導体装置を適用することで、様々な電子機器に本発明を実施できる。
100 単結晶半導体基板
101 絶縁層
102 異物
103 水素イオン
104 水素イオン
105 脆化領域
120 ベース基板
121 絶縁層
122 異物
124 水素イオン
125 脆化領域
130 ベース基板
131 単結晶半導体層
200 チャンバー壁
201 基板
202 ステージ軸
203 イオン源
204 バルブ
205 バルブ
206 イオン
400 チャンバー壁
401 基板
402 ステージ軸
403 イオン源
404 バルブ
405 バルブ
406 イオン
1205 単結晶半導体層
1206 単結晶半導体層
1207 ゲート絶縁層
1208 ゲート電極層
1209 ゲート電極層
1210 不純物元素
1211 マスク
1212a n型不純物領域
1212b n型不純物領域
1213 不純物元素
1214 マスク
1215a p型不純物領域
1215b p型不純物領域
1216a 側壁絶縁層
1216b 側壁絶縁層
1216c 側壁絶縁層
1216d 側壁絶縁層
1217 不純物元素
1218 マスク
1219a n型不純物領域
1219b n型不純物領域
1220a n型不純物領域
1220b n型不純物領域
1221 チャネル形成領域
1222 不純物元素
1223 マスク
1224a p型不純物領域
1224b p型不純物領域
1225a p型不純物領域
1225b p型不純物領域
1226 チャネル形成領域
1227 絶縁膜
1228 絶縁層
1229a 配線層
1229b 配線層
1230a 配線層
1230b 配線層
1231 トランジスタ
1232 トランジスタ
1233a ゲート絶縁層
1233b ゲート絶縁層
9101 本体
9102 表示部
9201 本体
9202 表示部
9301 本体
9302 表示部
9401 本体
9402 表示部
9701 表示部
9702 表示部
Claims (5)
- 単結晶半導体基板の一つの面上に絶縁層を形成し、
前記絶縁層を介して前記単結晶半導体基板の一つの面から第1の照射角度で第1の水素イオン照射工程を行い、
前記絶縁層を介して前記第1の水素イオン照射工程を行った前記単結晶半導体基板の一つの面から前記第1の照射角度と異なる第2の照射角度で第2の水素イオン照射工程を行うことで、前記単結晶半導体基板の一つの面から一定の深さに脆化領域を形成し、
前記単結晶半導体基板と支持基板とを前記絶縁層を挟んで重ね合わせた状態で前記脆化領域に亀裂を生じさせ、該亀裂を境に前記単結晶半導体基板を前記脆化領域で分離する熱処理を行い、前記単結晶半導体基板より単結晶半導体層を前記支持基板上に形成し、
前記第1の照射角度は前記単結晶半導体基板に対して25°以上85°以下であり、かつ前記第2の照射角度は前記単結晶半導体基板に対して95°以上155°以下であることを特徴とする半導体基板の作製方法。 - 単結晶半導体基板の一つの面上に絶縁層を形成し、
前記絶縁層を介して前記単結晶半導体基板の一つの面から第1の照射角度で第1の水素イオン照射工程を行い、
前記絶縁層を介して前記第1の水素イオン照射工程を行った前記単結晶半導体基板の一つの面に対し異物除去工程を行い、
異物除去工程を行った前記単結晶半導体基板の一つの面から前記第1の照射角度と異なる第2の照射角度で第2の水素イオン照射工程を行い、
前記単結晶半導体基板の一つの面から一定の深さに脆化領域を形成し、
前記単結晶半導体基板と支持基板とを前記絶縁層を挟んで重ね合わせた状態で前記脆化領域に亀裂を生じさせ、該亀裂を境に前記単結晶半導体基板を前記脆化領域で分離する熱処理を行い、前記単結晶半導体基板より単結晶半導体層を前記支持基板上に形成し、
前記第1の照射角度は前記単結晶半導体基板に対して25°以上85°以下であり、かつ前記第2の照射角度は前記単結晶半導体基板に対して95°以上155°以下であることを特徴とする半導体基板の作製方法。 - 請求項2において、前記異物除去工程として洗浄工程を行うことを特徴とする半導体基板の作製方法。
- 請求項1乃至3のいずれか一項において、
前記第1の水素イオン照射工程及び前記第2の水素イオン照射工程では、水素イオンは前記単結晶半導体基板全面に対して照射されることを特徴とする半導体基板の作製方法。 - 請求項1乃至4のいずれか一項に記載の半導体基板の作製方法において形成する前記単結晶半導体層を用いて半導体素子を形成することを特徴とする半導体装置の作製方法。
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JP2014011272A (ja) * | 2012-06-28 | 2014-01-20 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
KR101873203B1 (ko) * | 2011-12-15 | 2018-07-03 | 신에쯔 한도타이 가부시키가이샤 | Soi 웨이퍼의 제조방법 |
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FR2988516B1 (fr) | 2012-03-23 | 2014-03-07 | Soitec Silicon On Insulator | Procede d'implantation de fragilisation de substrats ameliore |
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JP2014011272A (ja) * | 2012-06-28 | 2014-01-20 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
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