JP2011228681A - 半導体基板の作製方法及び半導体装置の作製方法 - Google Patents
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
【解決手段】半導体基板の作製工程において、単結晶半導体基板に希ガスイオン照射工程、レーザー照射工程および水素イオン照射工程を行うことで、単結晶半導体基板の所定の深さに大きな結晶欠陥を含有した薄い脆化領域を形成し、剥離加熱工程を行うことで脆化領域より表面側の単結晶半導体層をベース基板に転載する。
【選択図】図1
Description
本実施の形態では、半導体基板の作製おいて、高機能な半導体集積回路を形成する半導体基板としての実用に耐えうる、平坦性の高い劈開面を有する単結晶半導体層を備えた半導体基板の作製方法について説明する。
本実施の形態では、実施の形態1において、単結晶半導体基板よりベース基板へ単結晶半導体層を接合する工程の異なる例を示す。従って、実施の形態1と同一部分又は同様な機能を有する部分の繰り返しの説明は省略する。
本実施の形態では、薄型で高性能な半導体素子を有する半導体集積回路を実装し、歩留まりよく作製することを目的とした半導体装置の作製方法の一例としてCMOS(相補型金属酸化物半導体:Complementary Metal Oxide Semiconductor)に関して図4及び図5を用いて説明する。なお、実施の形態1と同一部分又は同様な機能を有する部分の繰り返しの説明は省略する。
実施の形態3で作製された半導体装置を適用することで、様々な電子機器に本発明を実施できる。
102 絶縁層
103 希ガスイオン照射
104 第一の損傷領域
105 レーザー光
106 第二の損傷領域
107 水素イオン照射
108 脆化領域
109 レーザー光
110 単結晶半導体層
200 ベース基板
1205 単結晶半導体層
1206 単結晶半導体層
1207 ゲート絶縁層
1208 ゲート電極層
1209 ゲート電極層
1210 n型を付与する不純物元素
1211 マスク
1212a 第一のn型不純物領域
1212b 第一のn型不純物領域
1213 p型を付与する不純物元素
1214 マスク
1215a 第一のp型不純物領域
1215b 第一のp型不純物領域
1216a 側壁絶縁層
1216b 側壁絶縁層
1216c 側壁絶縁層
1216d 側壁絶縁層
1217 n型を付与する不純物元素
1218 マスク
1219a 第二のn型不純物領域
1219b 第二のn型不純物領域
1220a 第三のn型不純物領域
1220b 第三のn型不純物領域
1221 チャネル形成領域
1222 p型を付与する不純物元素
1223 マスク
1224a 第二のp型不純物領域
1224b 第二のp型不純物領域
1225a 第三のp型不純物領域
1225b 第三のp型不純物領域
1226 チャネル形成領域
1227 絶縁膜
1228 絶縁層
1229a 配線層
1229b 配線層
1230a 配線層
1230b 配線層
1231 トランジスタ
1232 トランジスタ
1233a ゲート絶縁層
1233b ゲート絶縁層
9101 本体
9102 表示部
9201 本体
9202 表示部
9301 本体
9302 表示部
9401 本体
9402 表示部
9701 表示部
9702 表示部
Claims (4)
- 単結晶半導体基板の一面に対して希ガスイオンを照射して前記単結晶半導体基板内に第一の損傷領域を形成し、
前記単結晶半導体基板の一面に対してレーザー光を照射して前記第一の損傷領域の一部を溶融し第二の損傷領域を形成し、
前記単結晶半導体基板の一面を介して前記第二の損傷領域に水素イオンを照射して前記単結晶半導体基板の一面から一定の深さに脆化領域を形成し、
前記単結晶半導体基板とベース基板とを、重ね合わせた状態で、前記脆化領域を劈開面として、前記単結晶半導体基板を前記脆化領域で分離する熱処理を行い、前記単結晶半導体基板より単結晶半導体層を前記ベース基板上に形成することを特徴とする半導体基板の作製方法。 - 単結晶半導体基板の一面に対して希ガスイオンを照射して前記単結晶半導体基板内に第一の損傷領域を形成し、
前記単結晶半導体基板の一面に対して第一のレーザー光を照射して前記第一の損傷領域の一部を溶融し第二の損傷領域を形成し、
前記単結晶半導体基板の一面を介して前記第二の損傷領域に水素イオンを照射して前記単結晶半導体基板の一面から一定の深さに脆化領域を形成し、
前記単結晶半導体基板の一面から第二のレーザー光を照射して前記単結晶半導体基板の一面と前記脆化領域間の領域を溶融し、
前記単結晶半導体基板とベース基板とを、重ね合わせた状態で、前記脆化領域を劈開面として、前記単結晶半導体基板を前記脆化領域で分離する熱処理を行い、前記単結晶半導体基板より単結晶半導体層を前記ベース基板上に形成することを特徴とする半導体基板の作製方法。 - 請求項1乃至2のいずれか一項において、前記希ガスイオンとしてヘリウムイオンが用いられることを特徴とする半導体基板の作製方法。
- 請求項1乃至3のいずれか一項に記載の半導体基板の作製方法において形成する前記単結晶半導体層を用いて半導体素子を形成することを特徴とする半導体装置の作製方法。
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US8637382B2 (en) * | 2011-08-01 | 2014-01-28 | Silicon Genesis Corporation | Layer transfer of films utilizing thermal flux regime for energy controlled cleaving |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1187668A (ja) * | 1997-09-04 | 1999-03-30 | Mitsubishi Materials Shilicon Corp | Soi基板の製造方法 |
JP2000124092A (ja) * | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
JP2009033135A (ja) * | 2007-06-26 | 2009-02-12 | Semiconductor Energy Lab Co Ltd | 半導体基板及び半導体基板の作製方法、半導体装置、電子機器 |
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JP4854866B2 (ja) * | 2001-04-27 | 2012-01-18 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
CN101652867B (zh) | 2007-04-06 | 2012-08-08 | 株式会社半导体能源研究所 | 光伏器件及其制造方法 |
CN101657907B (zh) | 2007-04-13 | 2012-12-26 | 株式会社半导体能源研究所 | 光伏器件及其制造方法 |
KR101440930B1 (ko) * | 2007-04-20 | 2014-09-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Soi 기판의 제작방법 |
SG160300A1 (en) | 2008-10-03 | 2010-04-29 | Semiconductor Energy Lab | Method for manufacturing soi substrate |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1187668A (ja) * | 1997-09-04 | 1999-03-30 | Mitsubishi Materials Shilicon Corp | Soi基板の製造方法 |
JP2000124092A (ja) * | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
JP2009033135A (ja) * | 2007-06-26 | 2009-02-12 | Semiconductor Energy Lab Co Ltd | 半導体基板及び半導体基板の作製方法、半導体装置、電子機器 |
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JP5805973B2 (ja) | 2015-11-10 |
US8324084B2 (en) | 2012-12-04 |
US20110244660A1 (en) | 2011-10-06 |
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