JP5498670B2 - 半導体基板の作製方法 - Google Patents

半導体基板の作製方法 Download PDF

Info

Publication number
JP5498670B2
JP5498670B2 JP2008175555A JP2008175555A JP5498670B2 JP 5498670 B2 JP5498670 B2 JP 5498670B2 JP 2008175555 A JP2008175555 A JP 2008175555A JP 2008175555 A JP2008175555 A JP 2008175555A JP 5498670 B2 JP5498670 B2 JP 5498670B2
Authority
JP
Japan
Prior art keywords
single crystal
crystal semiconductor
substrate
layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008175555A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009044136A5 (enExample
JP2009044136A (ja
Inventor
幸一郎 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2008175555A priority Critical patent/JP5498670B2/ja
Publication of JP2009044136A publication Critical patent/JP2009044136A/ja
Publication of JP2009044136A5 publication Critical patent/JP2009044136A5/ja
Application granted granted Critical
Publication of JP5498670B2 publication Critical patent/JP5498670B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/851—Division of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
JP2008175555A 2007-07-13 2008-07-04 半導体基板の作製方法 Expired - Fee Related JP5498670B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008175555A JP5498670B2 (ja) 2007-07-13 2008-07-04 半導体基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007183906 2007-07-13
JP2007183906 2007-07-13
JP2008175555A JP5498670B2 (ja) 2007-07-13 2008-07-04 半導体基板の作製方法

Publications (3)

Publication Number Publication Date
JP2009044136A JP2009044136A (ja) 2009-02-26
JP2009044136A5 JP2009044136A5 (enExample) 2011-08-11
JP5498670B2 true JP5498670B2 (ja) 2014-05-21

Family

ID=40253489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008175555A Expired - Fee Related JP5498670B2 (ja) 2007-07-13 2008-07-04 半導体基板の作製方法

Country Status (2)

Country Link
US (1) US7829431B2 (enExample)
JP (1) JP5498670B2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5700617B2 (ja) * 2008-07-08 2015-04-15 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US20100044827A1 (en) * 2008-08-22 2010-02-25 Kinik Company Method for making a substrate structure comprising a film and substrate structure made by same method
KR102481935B1 (ko) 2009-11-06 2022-12-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
JP5535610B2 (ja) * 2009-12-22 2014-07-02 三菱重工業株式会社 Ｓｏｉ半導体基板製造方法
JP5417399B2 (ja) * 2011-09-15 2014-02-12 信越化学工業株式会社 複合ウェーハの製造方法
FR3003997B1 (fr) * 2013-03-29 2015-03-20 Soitec Silicon On Insulator Procede de fabrication d'une structure composite
JP6359788B2 (ja) * 2016-03-10 2018-07-18 鴻海精密工業股▲ふん▼有限公司 蒸着マスク、蒸着マスク用マスク部材、及び蒸着マスクの製造方法と有機ｅｌ表示装置の製造方法
FR3071662B1 (fr) * 2017-09-25 2019-11-01 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de preparation d'une structure ayant une couche en materiau semi-conducteur monocristallin transferable et structure obtenue selon un tel procede

Family Cites Families (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2620240B2 (ja) * 1987-06-10 1997-06-11 株式会社日立製作所 液晶表示装置
JPS6461943A (en) 1987-09-02 1989-03-08 Seiko Epson Corp Semiconductor device and manufacture thereof
JPS6476034A (en) 1987-09-18 1989-03-22 Toshiba Corp Liquid crystal display device
JP2560765B2 (ja) 1988-01-20 1996-12-04 富士通株式会社 大面積半導体基板の製造方法
FR2632618A1 (fr) 1988-06-08 1989-12-15 Commissariat Energie Atomique Dispositif de transport sur coussin d'air avec guidage magnetique
JP2791084B2 (ja) 1989-03-08 1998-08-27 株式会社日立製作所 液晶表示装置
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH0590117A (ja) 1991-09-27 1993-04-09 Toshiba Corp 単結晶薄膜半導体装置
JP2814161B2 (ja) * 1992-04-28 1998-10-22 株式会社半導体エネルギー研究所 アクティブマトリクス表示装置およびその駆動方法
JPH0618926A (ja) 1992-07-02 1994-01-28 Sharp Corp 液晶表示用大型基板およびその製造方法
JPH07297377A (ja) 1994-04-21 1995-11-10 Mitsubishi Electric Corp 半導体装置およびその製造方法
FR2744285B1 (fr) * 1996-01-25 1998-03-06 Commissariat Energie Atomique Procede de transfert d'une couche mince d'un substrat initial sur un substrat final
JP3962465B2 (ja) * 1996-12-18 2007-08-22 キヤノン株式会社 半導体部材の製造方法
KR100304161B1 (ko) * 1996-12-18 2001-11-30 미다라이 후지오 반도체부재의제조방법
US6159825A (en) * 1997-05-12 2000-12-12 Silicon Genesis Corporation Controlled cleavage thin film separation process using a reusable substrate
US20020173000A1 (en) * 1997-05-30 2002-11-21 Stephane Renard Sodium channel receptor
JPH1126733A (ja) * 1997-07-03 1999-01-29 Seiko Epson Corp 薄膜デバイスの転写方法、薄膜デバイス、薄膜集積回路装置，アクティブマトリクス基板、液晶表示装置および電子機器
DE19737561C1 (de) * 1997-08-28 1999-04-15 Forschungszentrum Juelich Gmbh Mehrfarbensensor
JP3324469B2 (ja) * 1997-09-26 2002-09-17 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US6066860A (en) 1997-12-25 2000-05-23 Seiko Epson Corporation Substrate for electro-optical apparatus, electro-optical apparatus, method for driving electro-optical apparatus, electronic device and projection display device
US6320204B1 (en) * 1997-12-25 2001-11-20 Seiko Epson Corporation Electro-optical device in which an extending portion of a channel region of a semiconductor layer is connected to a capacitor line and an electronic apparatus including the electro-optical device
JP3719343B2 (ja) 1997-12-25 2005-11-24 セイコーエプソン株式会社 電気光学装置用基板、電気光学装置、電気光学装置の駆動方法及び電子機器並びに投射型表示装置
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
US6287941B1 (en) * 1999-04-21 2001-09-11 Silicon Genesis Corporation Surface finishing of SOI substrates using an EPI process
US6653209B1 (en) 1999-09-30 2003-11-25 Canon Kabushiki Kaisha Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
US6774010B2 (en) * 2001-01-25 2004-08-10 International Business Machines Corporation Transferable device-containing layer for silicon-on-insulator applications
JP4803884B2 (ja) * 2001-01-31 2011-10-26 キヤノン株式会社 薄膜半導体装置の製造方法
US6601783B2 (en) * 2001-04-25 2003-08-05 Dennis Chisum Abrasivejet nozzle and insert therefor
JP3946547B2 (ja) 2001-06-05 2007-07-18 シャープ株式会社 アクティブマトリクス基板および表示装置ならびに検出装置
JP3785067B2 (ja) * 2001-08-22 2006-06-14 株式会社東芝 半導体素子の製造方法
CN100403543C (zh) * 2001-12-04 2008-07-16 信越半导体株式会社 贴合晶片及贴合晶片的制造方法
JP4182323B2 (ja) 2002-02-27 2008-11-19 ソニー株式会社 複合基板、基板製造方法
US7119365B2 (en) * 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
JP4103447B2 (ja) 2002-04-30 2008-06-18 株式会社Ｉｈｉ 大面積単結晶シリコン基板の製造方法
KR100511656B1 (ko) 2002-08-10 2005-09-07 주식회사 실트론 나노 에스오아이 웨이퍼의 제조방법 및 그에 따라 제조된나노 에스오아이 웨이퍼
US6818529B2 (en) 2002-09-12 2004-11-16 Applied Materials, Inc. Apparatus and method for forming a silicon film across the surface of a glass substrate
US7508034B2 (en) * 2002-09-25 2009-03-24 Sharp Kabushiki Kaisha Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device
JP2004134675A (ja) 2002-10-11 2004-04-30 Sharp Corp Ｓｏｉ基板、表示装置およびｓｏｉ基板の製造方法
JP2004134672A (ja) * 2002-10-11 2004-04-30 Sony Corp 超薄型半導体装置の製造方法および製造装置、並びに超薄型の裏面照射型固体撮像装置の製造方法および製造装置
TW200415726A (en) * 2002-12-05 2004-08-16 Adv Lcd Tech Dev Ct Co Ltd Plasma processing apparatus and plasma processing method
US6759277B1 (en) 2003-02-27 2004-07-06 Sharp Laboratories Of America, Inc. Crystalline silicon die array and method for assembling crystalline silicon sheets onto substrates
JP3927165B2 (ja) 2003-07-03 2007-06-06 株式会社東芝 半導体装置
US7253040B2 (en) * 2003-08-05 2007-08-07 Sharp Kabushiki Kaisha Fabrication method of semiconductor device
US7199397B2 (en) * 2004-05-05 2007-04-03 Au Optronics Corporation AMOLED circuit layout
JP4407384B2 (ja) * 2004-05-28 2010-02-03 株式会社Ｓｕｍｃｏ Ｓｏｉ基板の製造方法
DE102004031708B4 (de) * 2004-06-30 2008-02-07 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Herstellen eines Substrats mit kristallinen Halbleitergebieten unterschiedlicher Eigenschaften
US7312487B2 (en) * 2004-08-16 2007-12-25 International Business Machines Corporation Three dimensional integrated circuit
US7298009B2 (en) * 2005-02-01 2007-11-20 Infineon Technologies Ag Semiconductor method and device with mixed orientation substrate
JP4934966B2 (ja) 2005-02-04 2012-05-23 株式会社Ｓｕｍｃｏ Ｓｏｉ基板の製造方法
US7674687B2 (en) * 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
US7655566B2 (en) * 2005-07-27 2010-02-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7911435B2 (en) * 2007-03-28 2011-03-22 Himax Technologies Limited Display and source driver thereof
SG178762A1 (en) 2007-04-13 2012-03-29 Semiconductor Energy Lab Display device, method for manufacturing display device, and soi substrate
WO2008142911A1 (en) 2007-05-18 2008-11-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN101681807B (zh) 2007-06-01 2012-03-14 株式会社半导体能源研究所 半导体器件的制造方法
US7776718B2 (en) * 2007-06-25 2010-08-17 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor substrate with reduced gap size between single-crystalline layers
JP5460984B2 (ja) * 2007-08-17 2014-04-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5452900B2 (ja) * 2007-09-21 2014-03-26 株式会社半導体エネルギー研究所 半導体膜付き基板の作製方法
TWI437696B (zh) * 2007-09-21 2014-05-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
JP5250228B2 (ja) * 2007-09-21 2013-07-31 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2009094488A (ja) * 2007-09-21 2009-04-30 Semiconductor Energy Lab Co Ltd 半導体膜付き基板の作製方法
WO2009072452A1 (en) * 2007-12-03 2009-06-11 Semiconductor Energy Laboratory Co., Ltd. Tft arrangement for display device

Also Published As

Publication number Publication date
US7829431B2 (en) 2010-11-09
JP2009044136A (ja) 2009-02-26
US20090017581A1 (en) 2009-01-15

Similar Documents

Publication Publication Date Title
JP5348942B2 (ja) 半導体装置の作製方法
JP5552216B2 (ja) 半導体装置
JP5498670B2 (ja) 半導体基板の作製方法
CN101335188B (zh) Soi基板的制造方法及半导体装置的制造方法
JP5512098B2 (ja) Ｓｏｉ基板の製造方法及び半導体装置の作製方法
JP5511172B2 (ja) 半導体装置の作製方法
KR101481974B1 (ko) Ｓｏｉ 기판의 제조 방법 및 반도체 장치의 제조 방법
JP5348926B2 (ja) Ｓｏｉ基板の製造方法
JP5159411B2 (ja) 表示装置
US20080316410A1 (en) Display device
JP2008294417A (ja) 半導体基板の作製方法、及び半導体装置の作製方法

Legal Events

Date Code Title Description
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20110510

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110623

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110623

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130625

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130627

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130724

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140304

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140310

R150 Certificate of patent or registration of utility model

Ref document number: 5498670

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees