JP5475217B2 - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
- Publication number
- JP5475217B2 JP5475217B2 JP2007041720A JP2007041720A JP5475217B2 JP 5475217 B2 JP5475217 B2 JP 5475217B2 JP 2007041720 A JP2007041720 A JP 2007041720A JP 2007041720 A JP2007041720 A JP 2007041720A JP 5475217 B2 JP5475217 B2 JP 5475217B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- pin
- semiconductor package
- esd
- gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
2 半田ボール
3、15、23、26 サージ吸収導体配線
4、9、10、11、12、15、16、17、19、20、21、22、25 配線
5 絶縁膜層
6 半導体チップ
7 ボンディング線
8 封止樹脂
13、18、24 配線層
14 貫通孔(空隙)
P1 ノンコネクト(NC)ピン
P2 接地電位ピン
P3 入出力ピン
P4 電源ピン
Claims (6)
- 複数の配線層から構成されたプリント基板を備えた半導体パッケージであって、前記複数の配線層の1つの中間配線層に空隙を設け、半導体チップに接続されないノンコネクトピンの配線とノイズ吸収配線とを前記空隙を挟んで対向するように設け、更に、
対向するノンコネクトピンの配線とノイズ吸収配線との空隙間隔(D)は、外部と接続するためのピンの間隔(L)よりも短いことを特徴とする半導体パッケージ。 - 前記ノイズ吸収配線は、接地電位配線または電源電位配線のいずれかに接続されていることを特徴とする請求項1に記載の半導体パッケージ。
- 前記ノンコネクトピンの配線は、外部と接続するためのピンに接続されているが、半導体チップには未接続、オープン状態であることを特徴とする請求項2に記載の半導体パッケージ。
- 前記外部と接続するためのピンは、半田ボールにより形成されていることを特徴とする請求項3に記載の半導体パッケージ。
- 複数の配線層から構成されたプリント基板は、前記複数の配線層の1つの中間配線層に空隙を設け、半導体チップに接続されないノンコネクトピンの配線とノイズ吸収配線とを前記空隙を挟んで対向するように配置し、そのプリント基板の1平面には半田ボールが実装され、他の平面には半導体チップが搭載され、
対向するノンコネクトピンの配線とノイズ吸収配線との空隙間隔(D)は、前記半田ボールの間隔(L)よりも短いことを特徴とする半導体装置。 - 前記ノイズ吸収配線は、接地電位配線または電源電位配線のいずれかに接続されていることを特徴とする請求項5に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007041720A JP5475217B2 (ja) | 2007-02-22 | 2007-02-22 | 半導体パッケージ |
US12/032,038 US20080203567A1 (en) | 2007-02-22 | 2008-02-15 | Semiconductor package and semiconductor device using the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007041720A JP5475217B2 (ja) | 2007-02-22 | 2007-02-22 | 半導体パッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008205332A JP2008205332A (ja) | 2008-09-04 |
JP5475217B2 true JP5475217B2 (ja) | 2014-04-16 |
Family
ID=39714950
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007041720A Expired - Fee Related JP5475217B2 (ja) | 2007-02-22 | 2007-02-22 | 半導体パッケージ |
Country Status (2)
Country | Link |
---|---|
US (1) | US20080203567A1 (ja) |
JP (1) | JP5475217B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7872346B1 (en) * | 2007-12-03 | 2011-01-18 | Xilinx, Inc. | Power plane and land pad feature to prevent human metal electrostatic discharge damage |
US8692390B2 (en) * | 2011-02-18 | 2014-04-08 | Chipbond Technology Corporation | Pyramid bump structure |
JP2013145489A (ja) * | 2012-01-16 | 2013-07-25 | Oki Electric Ind Co Ltd | 現金類処理装置、現金類処理方法、及びプログラム |
US10015916B1 (en) * | 2013-05-21 | 2018-07-03 | Xilinx, Inc. | Removal of electrostatic charges from an interposer via a ground pad thereof for die attach for formation of a stacked die |
US9960227B2 (en) | 2013-09-11 | 2018-05-01 | Xilinx, Inc. | Removal of electrostatic charges from interposer for die attachment |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04208559A (ja) * | 1990-11-30 | 1992-07-30 | Nec Corp | 半導体装置用パッケージ |
US5672911A (en) * | 1996-05-30 | 1997-09-30 | Lsi Logic Corporation | Apparatus to decouple core circuits power supply from input-output circuits power supply in a semiconductor device package |
JP2002198466A (ja) * | 2000-12-26 | 2002-07-12 | Nec Microsystems Ltd | 半導体装置 |
JP4094494B2 (ja) * | 2002-08-23 | 2008-06-04 | 新光電気工業株式会社 | 半導体パッケージ |
JP4961148B2 (ja) * | 2006-02-27 | 2012-06-27 | 株式会社デンソー | Icパッケージ、電子制御装置およびインターポーザ基板 |
-
2007
- 2007-02-22 JP JP2007041720A patent/JP5475217B2/ja not_active Expired - Fee Related
-
2008
- 2008-02-15 US US12/032,038 patent/US20080203567A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
JP2008205332A (ja) | 2008-09-04 |
US20080203567A1 (en) | 2008-08-28 |
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