JP4830609B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4830609B2 JP4830609B2 JP2006119778A JP2006119778A JP4830609B2 JP 4830609 B2 JP4830609 B2 JP 4830609B2 JP 2006119778 A JP2006119778 A JP 2006119778A JP 2006119778 A JP2006119778 A JP 2006119778A JP 4830609 B2 JP4830609 B2 JP 4830609B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Description
(第1実施形態)
図6は、本発明の第1実施形態に係る半導体装置の概略構成を示す図であり、(a)は導電性ボール実装面側から見た平面図、(b)は(a)のS3−S3線に沿う断面図である。図6(a)においては、便宜上、ソルダレジスト下にある補強用導体パターンを図示している。
次に、本発明の第2実施形態を、図10に基づいて説明する。図10は、第2実施形態に係る半導体装置100の概略構成を示す断面図である。図10は、図6(b)に対応している。
(第3実施形態)
次に、本発明の第3実施形態を、図11に基づいて説明する。図11は、第3実施形態に係る半導体装置100の主要部の概略構成を示す平面図であり(a)は一筆書き接続、(b)は環状接続の例を示している。なお、図11(a),(b)においては、便宜上、導電性ボール130、ソルダレジスト113を省略し、導体パターン112のうち、半導体チップ120とは電気的に接続されないもののみを図示している。
110・・・基板
111・・・基材
112・・・導体パターン
112b・・・(半導体チップに接続されない)接続部位
113・・・ソルダレジスト
114・・・補強用導体パターン
120・・・半導体チップ
130・・・導電性ボール
140・・・封止部材
Claims (11)
- 基材に導体パターンを配置してなる平面四角形の基板と、
前記基板の一面に実装された半導体チップと、
前記基板の半導体チップ実装面の裏面において、少なくとも前記基板の端部近傍に前記端部に沿って配置された外部接続用端子としての複数の導電性ボールと、
前記基板の、前記半導体チップ実装面上に配置され、前記基板に実装された前記半導体チップを封止する封止部材と、を含む半導体装置であって、
前記基板の厚さ方向における、前記導電性ボールの配置領域に対応する領域内において、外周角部を含む4つの局所部位のみに、電気的な接続機能を提供しない補強用導体パターンがそれぞれ配置され、
前記導電性ボールは、前記基板の裏面に配置された前記導体パターンの接続部位に接続されており、
前記接続部位には、前記接続部位の表面にメッキ層を形成するためのメッキ用導体パターンが接続され、
前記補強用導体パターンは、ベタパターンであり、前記基板の裏面において、少なくとも1つの前記接続部位を取り囲むとともに当該接続部位に接続された前記メッキ用導体パターンを取り囲むように配置されていることを特徴とする半導体装置。 - 前記補強用導体パターンに取り囲まれた前記接続部位が、電気的な接続機能を提供しないことを特徴とする請求項1に記載の半導体装置。
- 前記補強用導体パターンは、複数の前記接続部位を取り囲むように配置され、
全ての前記接続部位は、互いに接続されるとともに、前記補強用導体パターンに接続されていることを特徴とする請求項2に記載の半導体装置。 - 前記接続部位は、一筆書き接続とされていることを特徴とする請求項3に記載の半導体装置。
- 前記接続部位は、スター状接続とされていることを特徴とする請求項3に記載の半導体装置。
- 前記補強用導体パターンは、定電位に固定されていることを特徴とする請求項1〜5いずれか1項に記載の半導体装置。
- 前記補強用導体パターンは、前記基板の裏面において、前記4つの局所部位にそれぞれ配置されていることを特徴とする請求項1〜6いずれか1項に記載の半導体装置。
- 前記基板は、前記基材に前記導体パターンを多層に配置してなる多層基板であり、
前記補強用導体パターンは、前記裏面とは異なる層に配置されていることを特徴とする請求項7に記載の半導体装置。 - 前記導電性ボールの配置領域は、環状であり、
前記補強用導体パターンの配置領域は、前記外周角部からの長さが前記導電性ボールの配置領域の環状幅よりも短い範囲内の領域とされていることを特徴とする請求項1〜8いずれか1項に記載の半導体装置。 - 前記補強用導体パターンの配置領域は、前記基板の一辺の長さを1として、前記外周角部からの前記基板の端部に沿う長さが、0.05以上0.15以下の範囲内となる領域とされていることを特徴とする請求項9に記載の半導体装置。
- 前記補強用導体パターンの配置領域は、前記基板の一辺の長さを1として、前記外周角部からの前記基板の端部に沿う長さが、0.1となる領域とされていることを特徴とする請求項10に記載の半導体装置。
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JP2006119778A JP4830609B2 (ja) | 2006-04-24 | 2006-04-24 | 半導体装置 |
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JP2006119778A JP4830609B2 (ja) | 2006-04-24 | 2006-04-24 | 半導体装置 |
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JP2007294620A JP2007294620A (ja) | 2007-11-08 |
JP4830609B2 true JP4830609B2 (ja) | 2011-12-07 |
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Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009252916A (ja) * | 2008-04-04 | 2009-10-29 | Nec Electronics Corp | 多層配線基板、半導体パッケージ、および半導体パッケージの製造方法 |
JP5213034B2 (ja) * | 2008-07-09 | 2013-06-19 | Necインフロンティア株式会社 | Bgaパッケージ |
JP5262945B2 (ja) | 2009-04-15 | 2013-08-14 | 株式会社デンソー | 電子装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH11163214A (ja) * | 1997-11-27 | 1999-06-18 | Mitsui High Tec Inc | 半導体装置 |
JP4311774B2 (ja) * | 1998-03-11 | 2009-08-12 | 富士通株式会社 | 電子部品パッケージおよびプリント配線板 |
JP4341187B2 (ja) * | 2001-02-13 | 2009-10-07 | 日本電気株式会社 | 半導体装置 |
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