JP5463421B2 - ビットライン検知に基づく補償によりチャネル−フローティングゲート結合を低減するメモリプログラミング - Google Patents

ビットライン検知に基づく補償によりチャネル−フローティングゲート結合を低減するメモリプログラミング Download PDF

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JP5463421B2
JP5463421B2 JP2012540132A JP2012540132A JP5463421B2 JP 5463421 B2 JP5463421 B2 JP 5463421B2 JP 2012540132 A JP2012540132 A JP 2012540132A JP 2012540132 A JP2012540132 A JP 2012540132A JP 5463421 B2 JP5463421 B2 JP 5463421B2
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bit line
voltage
selected bit
level
latch
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Expired - Fee Related
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JP2012540132A
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Japanese (ja)
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JP2013512532A (ja
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ヤン リ
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SanDisk Technologies LLC
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SanDisk Technologies LLC
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
JP2012540132A 2009-11-24 2010-11-22 ビットライン検知に基づく補償によりチャネル−フローティングゲート結合を低減するメモリプログラミング Expired - Fee Related JP5463421B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/624,595 US8218381B2 (en) 2009-11-24 2009-11-24 Programming memory with sensing-based bit line compensation to reduce channel-to-floating gate coupling
US12/624,595 2009-11-24
PCT/US2010/057645 WO2011066228A1 (en) 2009-11-24 2010-11-22 Programming memory with sensing-based bit line compensation to reduce channel -to-floating gate coupling

Publications (2)

Publication Number Publication Date
JP2013512532A JP2013512532A (ja) 2013-04-11
JP5463421B2 true JP5463421B2 (ja) 2014-04-09

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JP2012540132A Expired - Fee Related JP5463421B2 (ja) 2009-11-24 2010-11-22 ビットライン検知に基づく補償によりチャネル−フローティングゲート結合を低減するメモリプログラミング

Country Status (7)

Country Link
US (2) US8218381B2 (zh)
EP (1) EP2504837B1 (zh)
JP (1) JP5463421B2 (zh)
KR (1) KR101702642B1 (zh)
CN (1) CN102714055B (zh)
TW (1) TW201133490A (zh)
WO (1) WO2011066228A1 (zh)

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US8218381B2 (en) 2009-11-24 2012-07-10 Sandisk Technologies Inc. Programming memory with sensing-based bit line compensation to reduce channel-to-floating gate coupling
US8174895B2 (en) * 2009-12-15 2012-05-08 Sandisk Technologies Inc. Programming non-volatile storage with fast bit detection and verify skip
US8891297B2 (en) 2011-11-01 2014-11-18 Micron Technology, Inc. Memory cell sensing
US8971141B2 (en) * 2012-06-28 2015-03-03 Sandisk Technologies Inc. Compact high speed sense amplifier for non-volatile memory and hybrid lockout
JP2015041402A (ja) * 2013-08-23 2015-03-02 株式会社東芝 不揮発性半導体記憶装置、及びデータ書き込み方法
JP2016054014A (ja) * 2014-09-03 2016-04-14 株式会社東芝 半導体記憶装置
US9875805B2 (en) 2015-01-23 2018-01-23 Sandisk Technologies Llc Double lockout in non-volatile memory
US9548130B2 (en) 2015-04-08 2017-01-17 Sandisk Technologies Llc Non-volatile memory with prior state sensing
US9570179B2 (en) 2015-04-22 2017-02-14 Sandisk Technologies Llc Non-volatile memory with two phased programming
JP2017111847A (ja) 2015-12-17 2017-06-22 株式会社東芝 半導体記憶装置
JP6490018B2 (ja) * 2016-02-12 2019-03-27 東芝メモリ株式会社 半導体記憶装置
US10366739B2 (en) * 2017-06-20 2019-07-30 Sandisk Technologies Llc State dependent sense circuits and sense operations for storage devices
US10037810B1 (en) 2017-06-27 2018-07-31 Sandisk Technologies Llc Method and apparatus for coupling up a voltage-setting transistor for a control line in a programming operation
US10636487B2 (en) * 2018-06-05 2020-04-28 Sandisk Technologies Llc Memory device with bit lines disconnected from NAND strings for fast programming
KR20200129239A (ko) 2019-05-07 2020-11-18 삼성전자주식회사 페이지 버퍼, 이를 포함하는 메모리 장치
KR20210011209A (ko) 2019-07-22 2021-02-01 삼성전자주식회사 비휘발성 메모리 장치 및 비휘발성 메모리 장치의 프로그램 방법
US11200952B2 (en) * 2019-07-22 2021-12-14 Samsung Electronics Co., Ltd. Non-volatile memory device
KR20210111051A (ko) 2020-03-02 2021-09-10 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 동작 방법

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JP3210259B2 (ja) * 1996-04-19 2001-09-17 株式会社東芝 半導体記憶装置及び記憶システム
JP3557078B2 (ja) * 1997-06-27 2004-08-25 株式会社東芝 不揮発性半導体記憶装置
KR100385226B1 (ko) * 2000-11-22 2003-05-27 삼성전자주식회사 프로그램 디스터브를 방지할 수 있는 플래시 메모리 장치및 그것을 프로그램하는 방법
JP2001243782A (ja) * 2001-02-13 2001-09-07 Toshiba Corp 不揮発性半導体記憶装置
JP3816022B2 (ja) 2002-05-28 2006-08-30 松下電器産業株式会社 半導体記憶装置
US6983428B2 (en) * 2002-09-24 2006-01-03 Sandisk Corporation Highly compact non-volatile memory and method thereof
US6987693B2 (en) * 2002-09-24 2006-01-17 Sandisk Corporation Non-volatile memory and method with reduced neighboring field errors
US6859397B2 (en) * 2003-03-05 2005-02-22 Sandisk Corporation Source side self boosting technique for non-volatile memory
US6956770B2 (en) 2003-09-17 2005-10-18 Sandisk Corporation Non-volatile memory and method with bit line compensation dependent on neighboring operating modes
US7064980B2 (en) 2003-09-17 2006-06-20 Sandisk Corporation Non-volatile memory and method with bit line coupled compensation
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US7173859B2 (en) 2004-11-16 2007-02-06 Sandisk Corporation Faster programming of higher level states in multi-level cell flash memory
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US7489554B2 (en) 2007-04-05 2009-02-10 Sandisk Corporation Method for current sensing with biasing of source and P-well in non-volatile storage
US7508715B2 (en) * 2007-07-03 2009-03-24 Sandisk Corporation Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing
US7599224B2 (en) * 2007-07-03 2009-10-06 Sandisk Corporation Systems for coarse/fine program verification in non-volatile memory using different reference levels for improved sensing
US7869273B2 (en) * 2007-09-04 2011-01-11 Sandisk Corporation Reducing the impact of interference during programming
JP4504405B2 (ja) * 2007-09-12 2010-07-14 株式会社東芝 半導体記憶装置
JP5178167B2 (ja) * 2007-12-04 2013-04-10 株式会社東芝 半導体記憶装置及びそのデータ書き込み方法
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US8218381B2 (en) 2009-11-24 2012-07-10 Sandisk Technologies Inc. Programming memory with sensing-based bit line compensation to reduce channel-to-floating gate coupling

Also Published As

Publication number Publication date
US20110122702A1 (en) 2011-05-26
JP2013512532A (ja) 2013-04-11
USRE45731E1 (en) 2015-10-06
US8218381B2 (en) 2012-07-10
EP2504837B1 (en) 2015-09-30
KR101702642B1 (ko) 2017-02-03
CN102714055A (zh) 2012-10-03
WO2011066228A1 (en) 2011-06-03
CN102714055B (zh) 2015-07-15
EP2504837A1 (en) 2012-10-03
TW201133490A (en) 2011-10-01
KR20120098801A (ko) 2012-09-05

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