JP5441007B2 - 電子部品内蔵基板の製造方法 - Google Patents
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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Description
まず、配線層22の前駆体(膜)である銅箔が貼付、塗布、蒸着等によって形成された樹脂シート(絶縁層21)を形成する(図2)。なお、銅箔としては、例えば、上述した配線層12,22,32,42に用いるものを使用でき、また、樹脂としては、例えば、上述した絶縁層11,21,31,41に用いるものを使用できる。この場合、予めCCL(Copper Clad Laminate)構造が形成された樹脂シートを用いてもよく、或いは、予めCCL構造が形成されていない未硬化又は半硬化状態の樹脂シートを用い、その樹脂シート上に電子部品50,51及びコア部材6を載置した後、硬化させることにより、それらを樹脂シート(絶縁層21,第1樹脂層)上に固定させてもよい。また、樹脂シートの厚さは、絶縁性が確保できる程度の薄さであることが好ましい。
次に、所定の厚さを有する金属板6’(コア部材6の前駆体である部材)を加工し、任意の形状に形成されたコア部材6を作成する(図3)。電子部品50,51が配置される金属板6’の部位、及びスルーホールが形成される金属板6’の部位をエッチング処理により取り除いて、電子部品50,51を配置する貫通口(開口)、及びスルーホールを形成する貫通口(開口)を形成し、これら以外の部位を残してコア部材6を形成する。なお、金属板6’に用いられる金属材料としては、例えば、上述したコア部材6に用いるものを使用でき、エッチング剤等により腐食可能な材料が挙げられる。
次に、電子部品内蔵基板2の最下層側の面に銅箔(配線層22)が貼付、塗布、蒸着等によって形成された樹脂シート(絶縁層21)上にコア部材6を接着する(図4)。具体的には、樹脂シート(絶縁層21)上にコア部材6を載置した後、熱プレス等により押圧することにより、樹脂シート(絶縁層21)上にコア部材6を接着する。押圧する温度は、樹脂シートに用いられる樹脂の軟化点付近であり、樹脂が硬化を開始する温度以下である。
樹脂シート(絶縁層21)上にコア部材6を接着した後、又は該接着と同時に樹脂シート(絶縁層21)上に電子部品50,51をいわゆるフェイスダウンの形態で接着し、電子部品50,51を固定する(図5)。
次いで、電子部品50及びコア部材6が絶縁層21上に接着固定された状態で、それらの電子部品50及びコア部材6を未硬化又は半硬化の樹脂(絶縁層31,第2樹脂層)で封入する。未硬化又は半硬化の樹脂(絶縁層31)上に、配線層32の前駆体(膜)となる金属箔(好ましくは銅箔)を、未硬化または半硬化の樹脂(絶縁層31)をラミネートプレスや熱プレス等を行って押圧する際に張り合わせる(挟み込む)ことにより、絶縁層31の硬化と同時に、絶縁層21,31、金属箔(配線層32)、電子部品50、及び、コア部材6を互いに密着させる(図6)。なお、銅箔(配線層22)及び金属箔(配線層32)は、略同じ厚さに形成することが好ましい。
それから、コア部材6の上面62に設けたアライメントマーク61,63と同時に形成した基板周辺部に位置するマーク(図示せず)を、例えばエッチング処理やレーザー加工等の、任意の方法で露出し、その基板周辺部に位置するマークを使用して電子部品50の電極位置52に、絶縁層21を貫通するように、レーザー処理、ブラスト処理、反応性イオンエッチング(RIE)処理等の任意の手法により、銅箔(配線層22)及び電子部品50のランド電極52間にビアホール26’を形成する。また、上述した処理方法により、銅箔(配線層22)及び電子部品51の端子間にビアホール26’を形成し、銅箔(配線層22)及びコア部材6間にビアホール25’を形成する(図7)。なお、電子部品50,51が内蔵された単位基板である個別基板(個片、個品)を複数有する集合基板(ワークボード、ワークシート)自体を基板周辺部に位置するマークとしてもよいし、集合基板の所定の部位に視認できるマークを設け、それを基板周辺部に位置するマークとしてもよい。
その後、形成されたビアホール25’,26’,35’,36’及びスルーホール7’に、無電解銅めっき等によりめっき等を塗布し、ビア導体25,26,35,36及びスルーホール部7の内壁周面の導体を形成する(図8)。
さらに、銅箔(配線層22)、及び金属箔(配線層32)を、例えばパターンめっき法を用いて、エッチング等によりパターニングして配線パターン(配線層22,32)を形成する(図9)。
次いで、パターニングされた配線層22,32上に、絶縁層11,41、及び配線層12,42の前駆体(膜)である金属箔(好ましくは銅箔)を順次配し、再び熱プレス等で押圧することにより、絶縁層11,21,31,41の硬化と同時に、配線層22,32、金属箔(配線層12,42)、絶縁層11,21,31,41、及び電子部品50,51間の密着や、配線層22,32、金属箔(配線層12,42)、絶縁層11,21,31,41、及びコア部材6間の密着を行う(図10)。
そして、絶縁層11,41のそれぞれを貫通するようにビアホールを形成し、さらに、めっき等を施してビア導体15,45を形成する(図11)。
次いで、金属箔(配線層12,42)をエッチング等によりパターニングして配線パターン(配線層12,42)を形成し、電子部品内蔵基板2を得る(図12)。
このようにして形成された電子部品内蔵基板2の最上面(最上層)に保護膜10を塗布した後、半田付け等の処理を用い、接合端部81を介して各受動部品8を載置して固定し、また、電子部品内蔵基板2の最下面(最下層)に保護膜10を塗布した後、出力端子9を設け、全体として回路を構成することにより、電子部品内蔵モジュール1を得る(図1)。
Claims (3)
- 電子部品が内蔵された電子部品内蔵基板の製造方法であって、
未硬化状態の第1樹脂層上に、コア部材を載置する工程と、
前記電子部品の端子が前記未硬化状態の第1樹脂層に接するように、該電子部品を該未硬化状態の第1樹脂層上に載置する工程と、
オートクレーブを用いて前記電子部品を前記第1樹脂層に押圧するとともに、前記未硬化状態の第1樹脂層を硬化する工程と、
前記硬化した第1樹脂層、前記コア部材、及び前記電子部品上に、未硬化状態の第2樹脂層を設ける工程と、
前記未硬化状態の第2樹脂層を硬化する工程と、
前記第1樹脂層を貫通して前記電子部品と電気的に接続するビアを形成する工程と、
を含む電子部品内蔵基板の製造方法。 - 前記コア部材にアライメントマークを形成する工程を含む、
請求項1記載の電子部品内蔵基板の製造方法。 - 前記コア部材の前駆体である部材に貫通口を形成する工程を含み、
前記アライメントマークを形成する工程を、前記貫通口を形成する工程と同時に実施する、
請求項2記載の電子部品内蔵基板の製造方法。
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JP5895635B2 (ja) * | 2012-03-16 | 2016-03-30 | 富士通株式会社 | 配線板の製造方法、配線板およびビアの構造 |
JP5117632B1 (ja) | 2012-08-21 | 2013-01-16 | 太陽誘電株式会社 | 高周波回路モジュール |
JP5285806B1 (ja) | 2012-08-21 | 2013-09-11 | 太陽誘電株式会社 | 高周波回路モジュール |
JP5400235B1 (ja) | 2012-11-09 | 2014-01-29 | 太陽誘電株式会社 | 電子部品内蔵基板 |
WO2014155535A1 (ja) | 2013-03-26 | 2014-10-02 | 富士機械製造株式会社 | 電子回路部品実装システム |
JP5888786B2 (ja) * | 2013-04-02 | 2016-03-22 | 太陽誘電株式会社 | 回路基板 |
JP5639242B2 (ja) * | 2013-04-12 | 2014-12-10 | 太陽誘電株式会社 | 電子部品内蔵基板 |
JP5422078B1 (ja) * | 2013-08-30 | 2014-02-19 | 太陽誘電株式会社 | 高周波回路モジュール |
JP6742682B2 (ja) * | 2014-09-03 | 2020-08-19 | 太陽誘電株式会社 | 多層配線基板 |
JP7394555B2 (ja) * | 2019-08-08 | 2023-12-08 | 三井・ケマーズ フロロプロダクツ株式会社 | 多層プリント配線板およびその製造方法 |
KR20230065438A (ko) * | 2021-11-04 | 2023-05-12 | 삼성디스플레이 주식회사 | 표시 장치 및 그것을 포함하는 전자 장치 |
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JP4551468B2 (ja) * | 2007-09-05 | 2010-09-29 | 太陽誘電株式会社 | 電子部品内蔵型多層基板 |
JP2009239247A (ja) * | 2008-03-27 | 2009-10-15 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
JP5093353B2 (ja) * | 2008-08-12 | 2012-12-12 | 株式会社村田製作所 | 部品内蔵モジュールの製造方法及び部品内蔵モジュール |
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