JP5437179B2 - 半導体パッケージ及びその製造方法 - Google Patents
半導体パッケージ及びその製造方法 Download PDFInfo
- Publication number
- JP5437179B2 JP5437179B2 JP2010147951A JP2010147951A JP5437179B2 JP 5437179 B2 JP5437179 B2 JP 5437179B2 JP 2010147951 A JP2010147951 A JP 2010147951A JP 2010147951 A JP2010147951 A JP 2010147951A JP 5437179 B2 JP5437179 B2 JP 5437179B2
- Authority
- JP
- Japan
- Prior art keywords
- upper substrate
- semiconductor element
- semiconductor package
- resin
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010147951A JP5437179B2 (ja) | 2010-06-29 | 2010-06-29 | 半導体パッケージ及びその製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010147951A JP5437179B2 (ja) | 2010-06-29 | 2010-06-29 | 半導体パッケージ及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012015192A JP2012015192A (ja) | 2012-01-19 |
| JP2012015192A5 JP2012015192A5 (enExample) | 2013-05-16 |
| JP5437179B2 true JP5437179B2 (ja) | 2014-03-12 |
Family
ID=45601311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010147951A Active JP5437179B2 (ja) | 2010-06-29 | 2010-06-29 | 半導体パッケージ及びその製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5437179B2 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5945326B2 (ja) * | 2012-07-30 | 2016-07-05 | パナソニック株式会社 | 放熱構造を備えた半導体装置 |
| KR102486784B1 (ko) | 2016-08-26 | 2023-01-09 | 삼성전기주식회사 | 반도체 패키지 |
| KR102554690B1 (ko) * | 2018-11-06 | 2023-07-13 | 삼성전자주식회사 | 반도체 패키지 |
| TWI733569B (zh) * | 2020-08-27 | 2021-07-11 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
| KR102921409B1 (ko) * | 2021-11-30 | 2026-02-02 | 삼성전기주식회사 | 반도체 패키지 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004014863A (ja) * | 2002-06-07 | 2004-01-15 | Mitsubishi Electric Corp | 電力用半導体装置 |
| JP3934565B2 (ja) * | 2003-02-21 | 2007-06-20 | 富士通株式会社 | 半導体装置 |
| JP2004363568A (ja) * | 2003-05-09 | 2004-12-24 | Matsushita Electric Ind Co Ltd | 回路素子内蔵モジュール |
| JP2009110979A (ja) * | 2007-10-26 | 2009-05-21 | Shinko Electric Ind Co Ltd | 発熱電子部品内装の配線基板及びその製造方法 |
-
2010
- 2010-06-29 JP JP2010147951A patent/JP5437179B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2012015192A (ja) | 2012-01-19 |
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