JP5436837B2 - 半導体装置内蔵基板の製造方法 - Google Patents

半導体装置内蔵基板の製造方法 Download PDF

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Publication number
JP5436837B2
JP5436837B2 JP2008280169A JP2008280169A JP5436837B2 JP 5436837 B2 JP5436837 B2 JP 5436837B2 JP 2008280169 A JP2008280169 A JP 2008280169A JP 2008280169 A JP2008280169 A JP 2008280169A JP 5436837 B2 JP5436837 B2 JP 5436837B2
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JP
Japan
Prior art keywords
insulating layer
semiconductor device
wiring pattern
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008280169A
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English (en)
Japanese (ja)
Other versions
JP2010109180A (ja
JP2010109180A5 (enExample
Inventor
敏男 小林
直 荒井
孝治 山野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2008280169A priority Critical patent/JP5436837B2/ja
Priority to US12/608,492 priority patent/US7981724B2/en
Publication of JP2010109180A publication Critical patent/JP2010109180A/ja
Publication of JP2010109180A5 publication Critical patent/JP2010109180A5/ja
Application granted granted Critical
Publication of JP5436837B2 publication Critical patent/JP5436837B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2008280169A 2008-10-30 2008-10-30 半導体装置内蔵基板の製造方法 Expired - Fee Related JP5436837B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008280169A JP5436837B2 (ja) 2008-10-30 2008-10-30 半導体装置内蔵基板の製造方法
US12/608,492 US7981724B2 (en) 2008-10-30 2009-10-29 Manufacturing method for semiconductor device embedded substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008280169A JP5436837B2 (ja) 2008-10-30 2008-10-30 半導体装置内蔵基板の製造方法

Publications (3)

Publication Number Publication Date
JP2010109180A JP2010109180A (ja) 2010-05-13
JP2010109180A5 JP2010109180A5 (enExample) 2011-09-22
JP5436837B2 true JP5436837B2 (ja) 2014-03-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008280169A Expired - Fee Related JP5436837B2 (ja) 2008-10-30 2008-10-30 半導体装置内蔵基板の製造方法

Country Status (2)

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US (1) US7981724B2 (enExample)
JP (1) JP5436837B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8929090B2 (en) * 2010-01-22 2015-01-06 Nec Corporation Functional element built-in substrate and wiring substrate
US9620455B2 (en) * 2010-06-24 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming anisotropic conductive film between semiconductor die and build-up interconnect structure
JP5884319B2 (ja) * 2011-07-06 2016-03-15 富士通株式会社 半導体装置の製造方法
JP2015032649A (ja) * 2013-08-01 2015-02-16 イビデン株式会社 配線板の製造方法および配線板
US10504865B2 (en) * 2017-09-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
JP7046639B2 (ja) * 2018-02-21 2022-04-04 新光電気工業株式会社 配線基板及びその製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2808038B2 (ja) 1990-09-11 1998-10-08 株式会社日立製作所 活動量センシングによる空気調和装置
JP2842378B2 (ja) 1996-05-31 1999-01-06 日本電気株式会社 電子回路基板の高密度実装構造
JP3524545B2 (ja) * 2002-01-23 2004-05-10 松下電器産業株式会社 回路部品内蔵モジュールの製造方法
TW577160B (en) * 2002-02-04 2004-02-21 Casio Computer Co Ltd Semiconductor device and manufacturing method thereof
JP3938921B2 (ja) * 2003-07-30 2007-06-27 Ｔｄｋ株式会社 半導体ｉｃ内蔵モジュールの製造方法
JP4441325B2 (ja) 2004-05-18 2010-03-31 新光電気工業株式会社 多層配線の形成方法および多層配線基板の製造方法
JP4285362B2 (ja) * 2004-08-17 2009-06-24 パナソニック株式会社 電子部品の実装構造および電子部品の製造方法
CN102098876B (zh) * 2006-04-27 2014-04-09 日本电气株式会社 用于电路基板的制造工艺
JP4121542B1 (ja) * 2007-06-18 2008-07-23 新光電気工業株式会社 電子装置の製造方法

Also Published As

Publication number Publication date
US20100112759A1 (en) 2010-05-06
JP2010109180A (ja) 2010-05-13
US7981724B2 (en) 2011-07-19

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