JP5436837B2 - 半導体装置内蔵基板の製造方法 - Google Patents

半導体装置内蔵基板の製造方法 Download PDF

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Publication number
JP5436837B2
JP5436837B2 JP2008280169A JP2008280169A JP5436837B2 JP 5436837 B2 JP5436837 B2 JP 5436837B2 JP 2008280169 A JP2008280169 A JP 2008280169A JP 2008280169 A JP2008280169 A JP 2008280169A JP 5436837 B2 JP5436837 B2 JP 5436837B2
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Japan
Prior art keywords
insulating layer
semiconductor device
wiring pattern
layer
substrate
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Expired - Fee Related
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JP2008280169A
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English (en)
Japanese (ja)
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JP2010109180A5 (enExample
JP2010109180A (ja
Inventor
敏男 小林
直 荒井
孝治 山野
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2008280169A priority Critical patent/JP5436837B2/ja
Priority to US12/608,492 priority patent/US7981724B2/en
Publication of JP2010109180A publication Critical patent/JP2010109180A/ja
Publication of JP2010109180A5 publication Critical patent/JP2010109180A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H01L2924/151—Die mounting substrate
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2008280169A 2008-10-30 2008-10-30 半導体装置内蔵基板の製造方法 Expired - Fee Related JP5436837B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008280169A JP5436837B2 (ja) 2008-10-30 2008-10-30 半導体装置内蔵基板の製造方法
US12/608,492 US7981724B2 (en) 2008-10-30 2009-10-29 Manufacturing method for semiconductor device embedded substrate

Applications Claiming Priority (1)

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JP2008280169A JP5436837B2 (ja) 2008-10-30 2008-10-30 半導体装置内蔵基板の製造方法

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JP2010109180A JP2010109180A (ja) 2010-05-13
JP2010109180A5 JP2010109180A5 (enExample) 2011-09-22
JP5436837B2 true JP5436837B2 (ja) 2014-03-05

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2011089936A1 (ja) * 2010-01-22 2013-05-23 日本電気株式会社 機能素子内蔵基板及び配線基板
US9620455B2 (en) * 2010-06-24 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming anisotropic conductive film between semiconductor die and build-up interconnect structure
JP5884319B2 (ja) * 2011-07-06 2016-03-15 富士通株式会社 半導体装置の製造方法
JP2015032649A (ja) * 2013-08-01 2015-02-16 イビデン株式会社 配線板の製造方法および配線板
US10504865B2 (en) * 2017-09-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
JP7046639B2 (ja) * 2018-02-21 2022-04-04 新光電気工業株式会社 配線基板及びその製造方法

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Publication number Priority date Publication date Assignee Title
JP2808038B2 (ja) 1990-09-11 1998-10-08 株式会社日立製作所 活動量センシングによる空気調和装置
JP2842378B2 (ja) 1996-05-31 1999-01-06 日本電気株式会社 電子回路基板の高密度実装構造
JP3524545B2 (ja) * 2002-01-23 2004-05-10 松下電器産業株式会社 回路部品内蔵モジュールの製造方法
TW577160B (en) * 2002-02-04 2004-02-21 Casio Computer Co Ltd Semiconductor device and manufacturing method thereof
JP3938921B2 (ja) * 2003-07-30 2007-06-27 Ｔｄｋ株式会社 半導体ｉｃ内蔵モジュールの製造方法
JP4441325B2 (ja) 2004-05-18 2010-03-31 新光電気工業株式会社 多層配線の形成方法および多層配線基板の製造方法
JP4285362B2 (ja) * 2004-08-17 2009-06-24 パナソニック株式会社 電子部品の実装構造および電子部品の製造方法
CN102098876B (zh) * 2006-04-27 2014-04-09 日本电气株式会社 用于电路基板的制造工艺
JP4121542B1 (ja) * 2007-06-18 2008-07-23 新光電気工業株式会社 電子装置の製造方法

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JP2010109180A (ja) 2010-05-13
US7981724B2 (en) 2011-07-19

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