JP5427366B2 - Ｓｏｉ基板の作製方法 - Google Patents

Ｓｏｉ基板の作製方法 Download PDF

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Publication number
JP5427366B2
JP5427366B2 JP2008108747A JP2008108747A JP5427366B2 JP 5427366 B2 JP5427366 B2 JP 5427366B2 JP 2008108747 A JP2008108747 A JP 2008108747A JP 2008108747 A JP2008108747 A JP 2008108747A JP 5427366 B2 JP5427366 B2 JP 5427366B2
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Prior art keywords
substrate
single crystal
film
silicon oxynitride
oxynitride film
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JP2008108747A
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Japanese (ja)
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JP2008294422A (ja
JP2008294422A5 (enExample
Inventor
舜平 山崎
英人 大沼
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008108747A priority Critical patent/JP5427366B2/ja
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Publication of JP2008294422A5 publication Critical patent/JP2008294422A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
JP2008108747A 2007-04-25 2008-04-18 Ｓｏｉ基板の作製方法 Active JP5427366B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008108747A JP5427366B2 (ja) 2007-04-25 2008-04-18 Ｓｏｉ基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007115993 2007-04-25
JP2007115993 2007-04-25
JP2008108747A JP5427366B2 (ja) 2007-04-25 2008-04-18 Ｓｏｉ基板の作製方法

Publications (3)

Publication Number Publication Date
JP2008294422A JP2008294422A (ja) 2008-12-04
JP2008294422A5 JP2008294422A5 (enExample) 2011-05-06
JP5427366B2 true JP5427366B2 (ja) 2014-02-26

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Family Applications (1)

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JP2008108747A Active JP5427366B2 (ja) 2007-04-25 2008-04-18 Ｓｏｉ基板の作製方法

Country Status (4)

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US (2) US7902034B2 (enExample)
EP (1) EP1986230A2 (enExample)
JP (1) JP5427366B2 (enExample)
KR (1) KR101447934B1 (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8115206B2 (en) * 2005-07-22 2012-02-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7847904B2 (en) 2006-06-02 2010-12-07 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic appliance
JP2008058809A (ja) * 2006-09-01 2008-03-13 Nuflare Technology Inc 基板カバー、荷電粒子ビーム描画装置及び荷電粒子ビーム描画方法
CN101281912B (zh) * 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
WO2008132904A1 (en) * 2007-04-13 2008-11-06 Semiconductor Energy Laboratory Co., Ltd. Photovoltaic device and method for manufacturing the same
US7763502B2 (en) * 2007-06-22 2010-07-27 Semiconductor Energy Laboratory Co., Ltd Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device
JP2009088500A (ja) * 2007-09-14 2009-04-23 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
US8236668B2 (en) * 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8193071B2 (en) * 2008-03-11 2012-06-05 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
JP5548395B2 (ja) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US20100038686A1 (en) * 2008-08-14 2010-02-18 Advanced Micro Devices, Inc. Soi substrates and devices on soi substrates having a silicon nitride diffusion inhibition layer and methods for fabricating
US8741740B2 (en) * 2008-10-02 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
CN101559627B (zh) * 2009-05-25 2011-12-14 天津大学 粒子束辅助单晶脆性材料超精密加工方法
JP5658916B2 (ja) * 2009-06-26 2015-01-28 株式会社半導体エネルギー研究所 半導体装置
US8735263B2 (en) 2011-01-21 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5704619B2 (ja) * 2012-06-15 2015-04-22 須賀　唯知 電子素子の封止方法及び基板接合体
FR2995445B1 (fr) * 2012-09-07 2016-01-08 Soitec Silicon On Insulator Procede de fabrication d'une structure en vue d'une separation ulterieure
JP2015233130A (ja) 2014-05-16 2015-12-24 株式会社半導体エネルギー研究所 半導体基板および半導体装置の作製方法
CN106159114A (zh) * 2015-04-23 2016-11-23 上海和辉光电有限公司 柔性显示器的封装方法
CN110391352B (zh) * 2018-04-17 2021-12-07 上海和辉光电股份有限公司 一种柔性显示器的封装方法和结构
JP6583897B1 (ja) * 2018-05-25 2019-10-02 ▲らん▼海精研股▲ふん▼有限公司 セラミック製静電チャックの製造方法
WO2025094696A1 (ja) * 2023-10-31 2025-05-08 富士フイルム株式会社 太陽電池の製造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
CN1244891C (zh) * 1992-08-27 2006-03-08 株式会社半导体能源研究所 有源矩阵显示器
TW299897U (en) * 1993-11-05 1997-03-01 Semiconductor Energy Lab A semiconductor integrated circuit
JPH08255762A (ja) * 1995-03-17 1996-10-01 Nec Corp 半導体デバイスの製造方法
CN1132223C (zh) * 1995-10-06 2003-12-24 佳能株式会社 半导体衬底及其制造方法
JP4103968B2 (ja) * 1996-09-18 2008-06-18 株式会社半導体エネルギー研究所 絶縁ゲイト型半導体装置
US6548382B1 (en) * 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
US6388652B1 (en) * 1997-08-20 2002-05-14 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device
EP1018153A1 (en) * 1997-08-29 2000-07-12 Sharon N. Farrens In situ plasma wafer bonding method
US6686623B2 (en) * 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
JP3697106B2 (ja) 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
JP2000012864A (ja) * 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
TW469484B (en) * 1999-03-26 2001-12-21 Semiconductor Energy Lab A method for manufacturing an electrooptical device
KR100711539B1 (ko) * 1999-06-10 2007-04-27 도요 고한 가부시키가이샤 반도체장치용 인터포저 형성용 클래드판, 반도체장치용인터포저 및 그 제조방법
JP2001358233A (ja) * 2000-06-15 2001-12-26 Hitachi Ltd 半導体集積回路装置および半導体集積回路装置の製造方法
JP2004134672A (ja) * 2002-10-11 2004-04-30 Sony Corp 超薄型半導体装置の製造方法および製造装置、並びに超薄型の裏面照射型固体撮像装置の製造方法および製造装置
JP3751972B2 (ja) * 2003-12-02 2006-03-08 有限会社ボンドテック 接合方法及びこの方法により作成されるデバイス並びに表面活性化装置及びこの装置を備えた接合装置
US20070110917A1 (en) * 2003-12-02 2007-05-17 Bondtech, Inc Bonding method, device formed by such method, surface activating unit and bonding apparatus comprising such unit
JP2004320050A (ja) 2004-06-29 2004-11-11 Sumitomo Mitsubishi Silicon Corp Ｓｏｉ基板及びその製造方法
FR2884966B1 (fr) * 2005-04-22 2007-08-17 Soitec Silicon On Insulator Procede de collage de deux tranches realisees dans des materiaux choisis parmi les materiaux semiconducteurs
JP5128761B2 (ja) * 2005-05-19 2013-01-23 信越化学工業株式会社 Ｓｏｉウエーハの製造方法
JP2007073878A (ja) 2005-09-09 2007-03-22 Shin Etsu Chem Co Ltd Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法
JP5116231B2 (ja) 2005-10-21 2013-01-09 住友ベークライト株式会社 プリント配線板、プリント配線板の製造方法及び多層プリント配線板
US7608521B2 (en) * 2006-05-31 2009-10-27 Corning Incorporated Producing SOI structure using high-purity ion shower

Also Published As

Publication number Publication date
US20110097872A1 (en) 2011-04-28
KR20080095748A (ko) 2008-10-29
US20080268583A1 (en) 2008-10-30
EP1986230A2 (en) 2008-10-29
US7902034B2 (en) 2011-03-08
JP2008294422A (ja) 2008-12-04
KR101447934B1 (ko) 2014-10-07
US8557676B2 (en) 2013-10-15

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