JP5415657B2 - 応力補償組成物、応力補償組成物によって導電性バンプを形成する方法、及び半導体部品 - Google Patents
応力補償組成物、応力補償組成物によって導電性バンプを形成する方法、及び半導体部品 Download PDFInfo
- Publication number
- JP5415657B2 JP5415657B2 JP2000201009A JP2000201009A JP5415657B2 JP 5415657 B2 JP5415657 B2 JP 5415657B2 JP 2000201009 A JP2000201009 A JP 2000201009A JP 2000201009 A JP2000201009 A JP 2000201009A JP 5415657 B2 JP5415657 B2 JP 5415657B2
- Authority
- JP
- Japan
- Prior art keywords
- stress compensation
- conductive
- epoxy resin
- layer
- conductive bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Epoxy Resins (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Compositions Of Macromolecular Compounds (AREA)
Description
11 基板
12 表面
13 ボンド・パッド
14 誘電層
16 再分布構造
17 導電層
18 誘電層(絶縁層)
19 穴
21 応力補償層
22 開口部
23 バンプ下メタライゼーション層
24 導電性ペースト
26 導電性バンプ
27 導電性ペースト
28 導電性バンプ
29 導電性バンプ
40 半導体部品
41 半田マスク層
42 バンプ下メタライゼーション層
43 開口部
44 導電性ペースト
46 導電性バンプ
47 応力補償層
49 開口部
51 導電性バンプ
52 バンプ構造
Claims (4)
- 導電性バンプを半導体ウェハの表面に備えその半導体ウェハ上に設けられる応力補償組成物であって、
第1の屈折率を有する芳香性エポキシ樹脂と、
石英またはシリカと、
第1の屈折率よりも低い第2の屈折率を有する脂肪性エポキシ樹脂と、
露光時にエポキシ組成物の重合を開始する光開始剤と
を含み、
エポキシ組成物は、エポキシ組成物の屈折率と石英またはシリカの屈折率とを一致させるように芳香性エポキシ樹脂と脂肪性エポキシ樹脂とを混合して生成されていることを特徴とする応力補償組成物。
- 請求項1記載の応力補償組成物を用いて導電性バンプを形成する方法であって、
主面(12)および前記主面上に設けられたボンド・パッド(13)を有する基板(11)と、前記ボンド・パッド(13)上に形成された第1導電性バンプ(26)とを設ける段階と、
前記応力補償組成物を用いて、前記主面および前記第1導電性バンプ(26)上に応力補償層(21)を形成する段階と、
前記第1導電性バンプを露出するため前記応力補償層(21)に開口を形成する段階と、
前記第1導電性バンプ上に第2導電性バンプを形成する段階と
を備えることを特徴とする方法。
- 請求項1記載の応力補償組成物を用いて導電性バンプを形成する方法であって、
主面(12)および前記主面上に設けられたボンド・パッド(13)を有する基板を設ける段階と、
前記応力補償組成物を用いて、前記主面および前記ボンド・パッド(13)上に応力補償層(21)を形成する段階と、
前記ボンド・パッド(13)を露出するため前記応力補償層(21)に開口を形成する段階と、
前記ボンド・パッド上に第1導電性バンプを形成する段階と
を備えることを特徴とする方法。
- 請求項2又は3記載の方法を用いて形成される導電性バンプを備えた半導体部品。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US348737 | 1999-07-06 | ||
US09/348,737 US6458622B1 (en) | 1999-07-06 | 1999-07-06 | Stress compensation composition and semiconductor component formed using the stress compensation composition |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001057374A JP2001057374A (ja) | 2001-02-27 |
JP5415657B2 true JP5415657B2 (ja) | 2014-02-12 |
Family
ID=23369311
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000201009A Expired - Fee Related JP5415657B2 (ja) | 1999-07-06 | 2000-07-03 | 応力補償組成物、応力補償組成物によって導電性バンプを形成する方法、及び半導体部品 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6458622B1 (ja) |
JP (1) | JP5415657B2 (ja) |
KR (1) | KR100718821B1 (ja) |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4239310B2 (ja) * | 1998-09-01 | 2009-03-18 | ソニー株式会社 | 半導体装置の製造方法 |
US6710454B1 (en) | 2000-02-16 | 2004-03-23 | Micron Technology, Inc. | Adhesive layer for an electronic apparatus having multiple semiconductor devices |
US6664176B2 (en) * | 2001-08-31 | 2003-12-16 | Infineon Technologies Ag | Method of making pad-rerouting for integrated circuit chips |
US6605524B1 (en) * | 2001-09-10 | 2003-08-12 | Taiwan Semiconductor Manufacturing Company | Bumping process to increase bump height and to create a more robust bump structure |
KR100429856B1 (ko) * | 2001-11-15 | 2004-05-03 | 페어차일드코리아반도체 주식회사 | 스터드 범프가 있는 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법 |
US6930032B2 (en) * | 2002-05-14 | 2005-08-16 | Freescale Semiconductor, Inc. | Under bump metallurgy structural design for high reliability bumped packages |
US6605491B1 (en) * | 2002-05-21 | 2003-08-12 | Industrial Technology Research Institute | Method for bonding IC chips to substrates with non-conductive adhesive |
JP2004014854A (ja) | 2002-06-07 | 2004-01-15 | Shinko Electric Ind Co Ltd | 半導体装置 |
FR2855650B1 (fr) * | 2003-05-30 | 2006-03-03 | Soitec Silicon On Insulator | Substrats pour systemes contraints et procede de croissance cristalline sur un tel substrat |
US20070105277A1 (en) | 2004-11-10 | 2007-05-10 | Stats Chippac Ltd. | Solder joint flip chip interconnection |
US7901983B2 (en) * | 2004-11-10 | 2011-03-08 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
US20060216860A1 (en) | 2005-03-25 | 2006-09-28 | Stats Chippac, Ltd. | Flip chip interconnection having narrow interconnection sites on the substrate |
US8216930B2 (en) * | 2006-12-14 | 2012-07-10 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
US8026128B2 (en) | 2004-11-10 | 2011-09-27 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
USRE47600E1 (en) | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
USRE44500E1 (en) | 2003-11-10 | 2013-09-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
US8674500B2 (en) | 2003-12-31 | 2014-03-18 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
US9029196B2 (en) | 2003-11-10 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
US7659633B2 (en) | 2004-11-10 | 2010-02-09 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
US8350384B2 (en) * | 2009-11-24 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
KR101286379B1 (ko) * | 2003-11-10 | 2013-07-15 | 스태츠 칩팩, 엘티디. | 범프-온-리드 플립 칩 인터커넥션 |
US8129841B2 (en) | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
US8574959B2 (en) * | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
US8076232B2 (en) | 2008-04-03 | 2011-12-13 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
US6890795B1 (en) * | 2003-12-30 | 2005-05-10 | Agency For Science, Technology And Research | Wafer level super stretch solder |
US7547969B2 (en) | 2004-10-29 | 2009-06-16 | Megica Corporation | Semiconductor chip with passivation layer comprising metal interconnect and contact pads |
US7745912B2 (en) * | 2005-03-25 | 2010-06-29 | Intel Corporation | Stress absorption layer and cylinder solder joint method and apparatus |
US8841779B2 (en) | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
US8048570B2 (en) | 2005-08-09 | 2011-11-01 | Polyplus Battery Company | Compliant seal structures for protected active metal anodes |
EP1917689B1 (en) | 2005-08-09 | 2017-11-08 | Polyplus Battery Company | Compliant seal structures for protected active metal anodes |
CN101278394B (zh) * | 2005-10-03 | 2010-05-19 | 罗姆股份有限公司 | 半导体装置 |
US7397121B2 (en) * | 2005-10-28 | 2008-07-08 | Megica Corporation | Semiconductor chip with post-passivation scheme formed over passivation layer |
US20080237822A1 (en) * | 2007-03-30 | 2008-10-02 | Raravikar Nachiket R | Microelectronic die having nano-particle containing passivation layer and package including same |
US7786001B2 (en) * | 2007-04-11 | 2010-08-31 | International Business Machines Corporation | Electrical interconnect structure and method |
US20090065555A1 (en) * | 2007-09-12 | 2009-03-12 | Stephen Leslie Buchwalter | Electrical interconnect forming method |
US7868457B2 (en) * | 2007-09-14 | 2011-01-11 | International Business Machines Corporation | Thermo-compression bonded electrical interconnect structure and method |
US8043893B2 (en) * | 2007-09-14 | 2011-10-25 | International Business Machines Corporation | Thermo-compression bonded electrical interconnect structure and method |
US20090127718A1 (en) * | 2007-11-15 | 2009-05-21 | Chen Singjang | Flip chip wafer, flip chip die and manufacturing processes thereof |
JP5337404B2 (ja) * | 2008-05-21 | 2013-11-06 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
KR100979497B1 (ko) * | 2008-06-17 | 2010-09-01 | 삼성전기주식회사 | 웨이퍼 레벨 패키지 및 그 제조방법 |
US9093448B2 (en) | 2008-11-25 | 2015-07-28 | Lord Corporation | Methods for protecting a die surface with photocurable materials |
JP5318222B2 (ja) * | 2008-11-25 | 2013-10-16 | ロード コーポレイション | 光硬化性材料でダイ表面を保護する方法 |
WO2011152255A1 (ja) * | 2010-06-02 | 2011-12-08 | 株式会社村田製作所 | Esd保護デバイス |
US9978656B2 (en) * | 2011-11-22 | 2018-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming fine-pitch copper bump structures |
EP2871455B1 (en) | 2013-11-06 | 2020-03-04 | Invensense, Inc. | Pressure sensor |
EP3367082A1 (en) | 2013-11-06 | 2018-08-29 | Invensense, Inc. | Pressure sensor |
JP6335513B2 (ja) * | 2014-01-10 | 2018-05-30 | 新光電気工業株式会社 | 半導体装置、半導体装置の製造方法 |
US9806046B2 (en) * | 2014-03-13 | 2017-10-31 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor device structure and manufacturing method |
EP3614115A1 (en) | 2015-04-02 | 2020-02-26 | InvenSense, Inc. | Pressure sensor |
US11225409B2 (en) | 2018-09-17 | 2022-01-18 | Invensense, Inc. | Sensor with integrated heater |
CN113785178A (zh) | 2019-05-17 | 2021-12-10 | 应美盛股份有限公司 | 气密性改进的压力传感器 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2187763A1 (en) * | 1994-04-15 | 1995-10-26 | Michael Alan Masse | Epoxidized low viscosity rubber toughening modifiers for epoxy resins |
US6020220A (en) * | 1996-07-09 | 2000-02-01 | Tessera, Inc. | Compliant semiconductor chip assemblies and methods of making same |
-
1999
- 1999-07-06 US US09/348,737 patent/US6458622B1/en not_active Expired - Lifetime
-
2000
- 2000-07-03 JP JP2000201009A patent/JP5415657B2/ja not_active Expired - Fee Related
- 2000-07-04 KR KR1020000037922A patent/KR100718821B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US6458622B1 (en) | 2002-10-01 |
KR20010049703A (ko) | 2001-06-15 |
KR100718821B1 (ko) | 2007-05-17 |
JP2001057374A (ja) | 2001-02-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5415657B2 (ja) | 応力補償組成物、応力補償組成物によって導電性バンプを形成する方法、及び半導体部品 | |
US5959363A (en) | Semiconductor device with improved encapsulating resin | |
US6593220B1 (en) | Elastomer plating mask sealed wafer level package method | |
JP4935670B2 (ja) | 半導体装置、並びにバッファーコート用樹脂組成物、ダイボンド用樹脂組成物、及び封止用樹脂組成物 | |
US5388328A (en) | Process for fabricating an interconnected multilayer board | |
CN107134414B (zh) | 半导体装置及其制造方法、倒装芯片型半导体装置及其制造方法 | |
US7473998B2 (en) | Method for forming bump protective collars on a bumped wafer | |
US6710446B2 (en) | Semiconductor device comprising stress relaxation layers and method for manufacturing the same | |
JP5618093B2 (ja) | 電子装置の製造方法、電子装置、電子装置パッケージの製造方法および電子装置パッケージ | |
KR101641608B1 (ko) | 광경화성 재료를 이용한 다이 표면의 보호방법 | |
US6396145B1 (en) | Semiconductor device and method for manufacturing the same technical field | |
KR20040088569A (ko) | B-스테이지 가공 가능한 언더필 캡슐화제 및 그의 적용방법 | |
US11923326B2 (en) | Bump structure and method of manufacturing bump structure | |
KR101138574B1 (ko) | 반도체 장치 | |
TWI225701B (en) | Process for forming bumps in adhesive layer in wafer level package | |
JP5157980B2 (ja) | 半導体素子封止体の製造方法および半導体パッケージの製造方法 | |
TWI768111B (zh) | 負型感光性樹脂組成物、半導體裝置及電子機器 | |
JPH01161850A (ja) | 半導体装置の製造方法 | |
JP2006098568A (ja) | 感光性樹脂組成物及びそれを用いた半導体装置 | |
Patel | Compliant wafer level package (CWLP) | |
JP2019062016A (ja) | 半導体装置の製造方法 | |
JPH11288971A (ja) | フィリップチップ実装工法 | |
JP4325531B2 (ja) | 樹脂封止型半導体装置 | |
JP3879973B2 (ja) | 半導体装置 | |
JP2006100562A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20041217 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070531 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20070531 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20080930 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100611 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100629 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100927 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110809 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20111109 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20111114 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120619 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121017 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20121024 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20121228 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130920 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131114 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |