JP5412667B2 - 積層ｌｓｉチップのシステム検査のための方法および検査システム - Google Patents

積層ｌｓｉチップのシステム検査のための方法および検査システム Download PDF

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Publication number
JP5412667B2
JP5412667B2 JP2008333816A JP2008333816A JP5412667B2 JP 5412667 B2 JP5412667 B2 JP 5412667B2 JP 2008333816 A JP2008333816 A JP 2008333816A JP 2008333816 A JP2008333816 A JP 2008333816A JP 5412667 B2 JP5412667 B2 JP 5412667B2
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Japan
Prior art keywords
chip
lsi chip
inspection
lsi
probe
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Expired - Fee Related
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JP2008333816A
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English (en)
Japanese (ja)
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JP2010156569A (ja
JP2010156569A5 (https=
Inventor
博 仲川
昌宏 青柳
義邦 岡田
祐教 松本
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National Institute of Advanced Industrial Science and Technology AIST
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National Institute of Advanced Industrial Science and Technology AIST
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Priority to JP2008333816A priority Critical patent/JP5412667B2/ja
Publication of JP2010156569A publication Critical patent/JP2010156569A/ja
Publication of JP2010156569A5 publication Critical patent/JP2010156569A5/ja
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Measuring Leads Or Probes (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2008333816A 2008-12-26 2008-12-26 積層ｌｓｉチップのシステム検査のための方法および検査システム Expired - Fee Related JP5412667B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008333816A JP5412667B2 (ja) 2008-12-26 2008-12-26 積層ｌｓｉチップのシステム検査のための方法および検査システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008333816A JP5412667B2 (ja) 2008-12-26 2008-12-26 積層ｌｓｉチップのシステム検査のための方法および検査システム

Publications (3)

Publication Number Publication Date
JP2010156569A JP2010156569A (ja) 2010-07-15
JP2010156569A5 JP2010156569A5 (https=) 2012-02-02
JP5412667B2 true JP5412667B2 (ja) 2014-02-12

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JP2008333816A Expired - Fee Related JP5412667B2 (ja) 2008-12-26 2008-12-26 積層ｌｓｉチップのシステム検査のための方法および検査システム

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JP (1) JP5412667B2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8378701B2 (en) * 2010-09-30 2013-02-19 Texas Instruments Incorporated Non-contact determination of joint integrity between a TSV die and a package substrate
JP5509170B2 (ja) * 2011-09-29 2014-06-04 力成科技股▲分▼有限公司 マルチチップ積層体の製造方法
JP2013088288A (ja) * 2011-10-18 2013-05-13 Fujitsu Semiconductor Ltd 検査装置及び検査システム
TWI493203B (zh) * 2012-05-23 2015-07-21 Advantest Corp A test vehicle, a good judgment device, and a good judgment method
JP5967713B2 (ja) * 2012-12-13 2016-08-10 国立研究開発法人産業技術総合研究所 積層型ｌｓｉチップの絶縁膜の検査方法及び積層型ｌｓｉチップの製造方法
KR101901076B1 (ko) * 2014-07-17 2018-09-20 가부시키가이샤 니혼 마이크로닉스 반도체 모듈, 전기적 접속체 및 검사 장치
JP6654096B2 (ja) * 2016-04-29 2020-02-26 日本電子材料株式会社 プローブカード
WO2022204277A1 (en) * 2021-03-23 2022-09-29 Nielson Scientific Llc Cryogenic probe card
KR102850097B1 (ko) * 2022-02-10 2025-08-26 삼성디스플레이 주식회사 발광 소자 테스트 장치

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6249239U (https=) * 1985-09-13 1987-03-26
JPH07111995B2 (ja) * 1987-09-02 1995-11-29 東京エレクトロン株式会社 プローブ装置
JPH02103482A (ja) * 1988-10-13 1990-04-16 Matsushita Graphic Commun Syst Inc 集積回路装置
US5278961A (en) * 1990-02-22 1994-01-11 Hewlett-Packard Company Physical address to logical address translator for memory management units
JPH05275504A (ja) * 1992-01-16 1993-10-22 Toshiba Corp プローブカード
FR2700063B1 (fr) * 1992-12-31 1995-02-10 Sgs Thomson Microelectronics Procédé de test de puces de circuit intégré et dispositif intégré correspondant.
JPH1038924A (ja) * 1996-07-25 1998-02-13 Advantest Corp プローブカード
JP2001144149A (ja) * 1999-11-12 2001-05-25 Sony Corp 半導体測定冶具
US6718498B2 (en) * 2001-06-04 2004-04-06 Hewlett-Packard Development Company, L.P. Method and apparatus for the real time manipulation of a test vector to access the microprocessor state machine information using the integrated debug trigger

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Publication number Publication date
JP2010156569A (ja) 2010-07-15

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