JP5406331B2 - プログラマブルロジックデバイスのための特殊処理ブロック - Google Patents
プログラマブルロジックデバイスのための特殊処理ブロック Download PDFInfo
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
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- G06F7/523—Multiplying only
- G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
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Description
本出願は、2006年2月9日および2006年4月4日にそれぞれ出願された同時係属であり、同一出願人に係る米国仮特許出願第60/772,197号および第60/789,535号の利益を主張する。各々は、本明細書においてそのそれぞれの全容が参考により援用される。
本発明は、プログラマブルロジックデバイス(PLD)に関し、より詳細には、そのようなデバイスに含まれ得る特殊処理ブロックに関する。
プログラマブルロジックデバイスのための特殊処理ブロックであって、該特殊処理ブロックは、
複数の基本処理ユニットを備え、該基本処理ユニットの各々は、
複数の乗算器と、
該複数の乗算器の全てによって生成された部分積を、一演算において、加算するための回路網と
を含む、特殊処理ブロック。
上記基本処理ユニットの各々が、上記部分積を加算する前にシフトするための回路網をさらに含む、項目1に記載の特殊処理ブロック。
上記特殊処理ブロックの出力を該特殊処理ブロックの入力にフィードバックするためのループバック回路網をさらに備える、項目1に記載の特殊処理ブロック。
上記ループバック回路網が、上記特殊処理ブロックを適合フィルタとして構成するために使用される、項目3に記載の特殊処理ブロック。
複数のソースからの入力を整列させるための入力前処理回路網をさらに備える、項目3に記載の特殊処理ブロック。
上記複数のソースが、上記特殊処理ブロックへの入力および該特殊処理ブロックの出力を含む、項目5に記載の特殊処理ブロック。
上記複数のソースが、他の上記特殊処理ブロックの出力をさらに含む、項目6に記載の特殊処理ブロック。
上記入力前処理回路網が、上記入力を登録するためのレジスタを含む、項目5に記載の特殊処理ブロック。
上記レジスタが、データを上記複数の乗算器の各々に順次入力するためにチェーン状にされている、項目8に記載の特殊処理ブロック。
上記レジスタが、上記乗算器の群の間における遅延を上記チェーンにおいて導入するための追加のレジスタを含む、項目9に記載の特殊処理ブロック。
出力段をさらに備えており、
該出力段は、
該特殊処理ブロックのうちの少なくとも1つのサブセットの各々に対して複数の加算器を含み、該複数の加算器は、(a)複数の上記基本処理ユニットを含む乗算演算の出力と、(b)(1)該基本処理ユニットのうちの少なくとも1つを含む乗算演算と、(2)該特殊処理ブロックのうちの他の1つにおける他の出力段における他の該複数の加算器からカスケードされる対応出力との合計とのうちの1つを出力として提供するように適合可能である、項目1に記載の特殊処理ブロック。
上記出力段が、上記加算器のうちの1つと協働して、累積機能を提供するためのフィードバック回路網をさらに含む、項目11の特殊処理ブロック。
上記ブロック出力の複数のビット範囲のうちの1つをシフトされた出力として選択するための回路網をさらに備える、項目11に記載の特殊処理ブロック。
シフトされた出力を選択するための上記回路網が、上記出力段および上記複数の基本ユニット間のパイプラインレジスタ段を含む、項目13に記載の特殊処理ブロック。
上記複数のビット範囲を結合出力へと結合するための回路網、および、(a)該複数のビット範囲のうちの1つと、(b)該結合出力とのうちの1つを選択するための回路網をさらに備える、項目13に記載の特殊処理ブロック。
上記結合するための回路網が、OR回路網を含み、上記結合出力が、上記ブロック出力のローテートを含む、項目15に記載の特殊処理ブロック。
上記基本処理ユニットの各々が2つの乗算器を含み、
該複数の基本処理ユニットが、2つずつの該基本処理ユニットの群に構成された少なくとも2つの該基本処理ユニットを含み、
上記出力段における上記複数の加算器が、該群の各々に対して2つの加算器を含み、該加算器の各々が、第1の加算器幅を有し、該2つの加算器が、(a)該少なくとも2つの基本処理ユニットを含む上記乗算演算の上記出力を提供するために該第1の加算器幅より広い幅を有する単一の加算と、(b)該基本処理ユニットのうちの少なくとも1つを含む上記乗算演算を提供するために該第1の加算器幅の最大幅を有する第1の加算、および、(1)該乗算演算と、(2)上記特殊処理ブロックのうちの他の1つにおける他の出力段における他の該複数の加算器からカスケードされる上記対応出力との上記合計を提供するために該第1の加算器幅の最大幅を有する第2の加算とのうちの1つを実行するように構成可能である、項目11に記載の特殊処理ブロック。
上記出力段および上記基本処理ユニット間のパイプラインレジスタ段をさらに備えており、
該パイプラインレジスタ段が、上記加算器幅より広い幅を有する上記加算を実行するために該基本ユニットによるデータ出力を整列させるように適合可能である、項目17に記載の特殊処理ブロック。
出力段および上記基本処理ユニット間のパイプラインレジスタ段をさらに備える、項目1に記載の特殊処理ブロック。
項目1の特殊処理ブロックを備える、プログラマブルロジックデバイス。
処理回路網と、
該処理回路網に結合されているメモリと、
該処理回路網および該メモリに結合されている、項目20に記載のプログラマブルロジックデバイスと
を備える、デジタル処理システム。
項目20に記載のプログラマブルロジックデバイスが上に取り付けられている、プリント基板。
メモリ回路網であって、上記プリント基板上に取り付けられており、かつ上記プログラマブルロジックデバイスに結合されている、メモリ回路網をさらに備える、項目22に記載のプリント基板。
処理回路網であって、上記プリント基板上に取り付けらており、かつ上記メモリ回路網に結合されている、処理回路網をさらに備える、項目23に記載のプリント基板。
項目1に記載の特殊処理ブロックを備える、集積回路デバイス。
処理回路網と、
該処理回路網に結合されているメモリと、
該処理回路網および該メモリに結合されている、項目25に記載の集積回路デバイスと
を備える、デジタル処理システム。
項目26に記載の集積回路デバイスが上に取り付けられている、プリント基板。
メモリ回路網であって、上記プリント基板上に取り付けらており、かつ上記プログラマブルロジックデバイスに結合されている、メモリ回路網をさらに備える、項目27に記載のプリント基板。
処理回路網であって、上記プリント基板上に取り付けられており、かつ上記メモリ回路網に結合されている処理回路網をさらに備える、項目28に記載のプリント基板。
Real Result=Re[(a+jb)×(c+jd)]=(ac−bd)
Imag Result=Im[(a+jb)×(c+jd)]=(ad+bc)
である18×18複素数乗算を考慮する。この複素数演算は、4つの18×18乗算を必要とし、従って、8つの18ビット入力を必要とする。しかしながら、4つの固有18ビット共有入力しかないため、入力マルチプレクシング段13は、入力a,b,cおよびdを取得し、かつ必要な複製を実行する。それは、その4つの入力が、実計算および虚計算の各々に対する正確な乗算器入力に適切にルートされるようにである。同様に、9および12ビットモード動作に対して、入力プレMUX段11および/または入力マルチプレクシング段13は、正確な結果を得るために入力ビットの正確な整列を保証する。
11 入力プレMUX段
12 入力レジスタ段
13 入力マルチプレクシング段
14 乗算段
15 パイプラインレジスタ段
16 加算器/出力段
17 ループバック
Claims (10)
- プログラマブルロジックデバイスのための特殊処理ブロックであって、該特殊処理ブロックは、有限インパルス応答(FIR)フィルタを形成するように適合可能であり、該特殊処理ブロックは、
複数の基本処理ユニットであって、該複数の基本処理ユニットの各々は、
複数の部分積生成器であって、該複数の部分積生成器のうちのそれぞれ1つは、それぞれの部分積を表すそれぞれの複数のベクトルを提供する、複数の部分積生成器と、
該複数の部分積生成器の全てによって生成された該複数のベクトルによって表された部分積を、一演算において、加算するための回路網であって、該複数の部分積生成器のうちのいずれの部分積生成器の部分積も個別には出力されず、該加算するための回路網は、該複数の部分積生成器の全ての部分積の全ての合計のみを出力する、加算するための回路網と
を含む、複数の基本処理ユニットと、
該複数の部分積生成器への入力として該FIRフィルタの係数を入力するための第1の複数の入力レジスタと、
該FIRフィルタにデータを入力するための第2の複数の入力レジスタであって、該複数のレジスタは、該複数の部分積生成器の各々にデータを順次入力するためにチェーン状にされている、第2の複数の入力レジスタと、
(1)該複数の基本処理ユニットのうちの2つの基本処理ユニットを必要とする演算と、(2)該複数の特殊処理ブロックのうちの第1の他の特殊処理ブロックからカスケードされる対応出力とを出力として結合するための出力段であって、該出力段は、該複数の特殊処理ブロックのうちの第2の他の特殊処理ブロックにおいて第2の他の出力段にカスケードするために該出力を登録するための出力カスケードレジスタを含む、出力段と
を含み、
該第2の複数の入力レジスタは、該複数の特殊処理ブロックのうちの該第2の他の特殊処理ブロックにおいて、該第2の複数の入力レジスタが対応する第2の複数の入力レジスタにチェーン状にされているとき、該出力カスケードレジスタに対して補償するための遅延レジスタを含む、特殊処理ブロック。 - 前記遅延レジスタは、複数の遅延レジスタを含み、該複数の遅延レジスタは、前記複数の基本処理ユニットの各対に対して1つの遅延レジスタを含む、請求項1に記載の特殊処理ブロック。
- 前記複数の基本処理ユニットの各々は、それぞれの複数のベクトルの各々が前記加算するための回路網によって加算される前に、該それぞれの複数のベクトルの各々を圧縮する圧縮器回路網をさらに含む、請求項1に記載の特殊処理ブロック。
- 前記出力段は、複数の加算器をさらに含み、該複数の加算器は、(1)前記複数の基本処理ユニットのうちの2つの基本処理ユニットを必要とする前記演算と、(2)前記複数の特殊処理ブロックのうちの第1の他の特殊処理ブロックからカスケードされた前記対応出力との合計を出力として提供するように適合可能である、請求項1に記載の特殊処理ブロック。
- 有限インパルス応答(FIR)フィルタを形成するように適合可能であるプログラマブルロジックデバイスであって、該プログラマブルロジックデバイスは、
少なくとも1つの特殊処理ブロックであって、該少なくとも1つの特殊処理ブロックの各々は、
複数の基本処理ユニットであって、該複数の基本処理ユニットの各々は、
複数の部分積生成器であって、該複数の部分積生成器のうちのそれぞれ1つは、それぞれの部分積を表すそれぞれの複数のベクトルを提供する、複数の部分積生成器と、
該複数の部分積生成器の全てによって生成された該複数のベクトルによって表された部分積を、一演算において、加算するための回路網であって、該複数の部分積生成器のうちのいずれの部分積生成器の部分積も個別には出力されず、該加算するための回路網は、該複数の部分積生成器の全ての部分積の全ての合計のみを出力する、加算するための回路網と
を含む、複数の基本処理ユニットと、
(1)該複数の基本処理ユニットのうちの2つの基本処理ユニットを必要とする演算と、(2)該複数の特殊処理ブロックのうちの第1の他の特殊処理ブロックにおいて第1の他の出力段からカスケードされる対応出力とを出力として結合するための出力段と
を含み、
該少なくとも1つの特殊処理ブロックの各々は、
該複数の特殊処理ブロックのうちの第2の他の特殊処理ブロックにおいて、第2の他の出力段にカスケードするために該出力を登録するための出力カスケードレジスタをさらに含み、
該プログラマブルロジックデバイスは、
該FIRフィルタにデータを入力するための第1の複数の入力レジスタであって、該複数のレジスタは、該複数の乗算器の各々にデータを順次入力するためにチェーン状にされている、第1の複数の入力レジスタと、
該第1の複数の入力レジスタが、該複数の特殊処理ブロックのうちの該第2の他の特殊処理ブロックにおいて対応する第1の複数の入力レジスタにチェーン状にされているとき、該出力カスケードレジスタを補償するために該第1の複数の入力レジスタにチェーン状にされる遅延レジスタと
をさらに含む、プログラマブルロジックデバイス。 - 前記遅延レジスタは、複数の遅延レジスタを含み、該複数の遅延レジスタは、前記複数の基本処理ユニットの各対に対して1つの遅延レジスタを含む、請求項5に記載のプログラマブルロジックデバイス。
- 前記複数の基本処理ユニットの各々は、それぞれの複数のベクトルの各々が前記加算するための回路網によって加算される前に、該それぞれの複数のベクトルの各々を圧縮する圧縮器回路網をさらに含む、請求項5に記載のプログラマブルロジックデバイス。
- 前記出力段は、複数の加算器を含み、該複数の加算器は、(1)前記複数の基本処理ユニットのうちの2つの基本処理ユニットを必要とする前記演算と、(2)前記複数の特殊処理ブロックのうちの前記第1の他の特殊処理ブロックにおいて、前記第1の他の出力段からカスケードされた前記対応出力との合計を出力として提供するように適合可能である、請求項5に記載のプログラマブルロジックデバイス。
- 前記第1の複数の入力レジスタと前記遅延レジスタとは、前記特殊処理ブロックに含まれている、請求項5に記載のプログラマブルロジックデバイス。
- 前記複数の部分積生成器への入力として、前記FIRフィルタの係数を入力するための第2の複数の入力レジスタをさらに含む、請求項5に記載のプログラマブルロジックデバイス。
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US77219706P | 2006-02-09 | 2006-02-09 | |
US60/772,197 | 2006-02-09 | ||
US78953506P | 2006-04-04 | 2006-04-04 | |
US60/789,535 | 2006-04-04 | ||
US11/447,472 US8266199B2 (en) | 2006-02-09 | 2006-06-05 | Specialized processing block for programmable logic device |
US11/447,472 | 2006-06-05 |
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US20070185952A1 (en) | 2007-08-09 |
JP2012157066A (ja) | 2012-08-16 |
CN102386912A (zh) | 2012-03-21 |
EP1819049B1 (en) | 2012-09-26 |
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