JP5393728B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5393728B2 JP5393728B2 JP2011124895A JP2011124895A JP5393728B2 JP 5393728 B2 JP5393728 B2 JP 5393728B2 JP 2011124895 A JP2011124895 A JP 2011124895A JP 2011124895 A JP2011124895 A JP 2011124895A JP 5393728 B2 JP5393728 B2 JP 5393728B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- terminal
- snubber
- igbt
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 140
- 238000001514 detection method Methods 0.000 claims description 28
- 238000012544 monitoring process Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 claims description 8
- 230000002457 bidirectional effect Effects 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 description 28
- 238000009499 grossing Methods 0.000 description 28
- 238000010586 diagram Methods 0.000 description 24
- 238000011084 recovery Methods 0.000 description 15
- 239000000758 substrate Substances 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 13
- 230000000694 effects Effects 0.000 description 7
- 230000020169 heat generation Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010037660 Pyrexia Diseases 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000013138 pruning Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000036413 temperature sense Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/06—Circuits specially adapted for rendering non-conductive gas discharge tubes or equivalent semiconductor devices, e.g. thyratrons, thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12035—Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/34—Snubber circuits
- H02M1/344—Active dissipative snubbers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Power Conversion In General (AREA)
- Electronic Switches (AREA)
- Inverter Devices (AREA)
Description
図1は、本発明の実施の形態1に係る半導体装置の構成を示す回路図である。図1に示すように、本実施の形態に係る半導体装置は、破線で囲まれた半導体装置51と、コントローラ52からの制御に基づいて半導体装置51を駆動制御するドライブ回路53と、ドライブ回路53に直流電圧(電力)を供給する電力供給部54と、半導体装置51と接続された負荷部55とを備える。
図6は、本発明の実施の形態2に係る半導体装置の構成を示す回路図である。なお、以下、本実施の形態に係る半導体装置についての説明において、実施の形態1で説明した構成要素と類似するものについては同じ符号を付して説明を省略する。
図7は、本発明の実施の形態3に係る半導体装置の構成を示す回路図である。図8は、本実施の形態に係る半導体装置51の構成を示す平面図である。図9は、本実施の形態に係る第2スナバデバイスSD2の構成の一例を示す平面図である。なお、以下、本実施の形態に係る半導体装置についての説明において、実施の形態2で説明した構成要素と類似するものについては同じ符号を付して説明を省略する。
図10は、本発明の実施の形態4に係る半導体装置の構成を示す回路図である。なお、以下、本実施の形態に係る半導体装置についての説明において、実施の形態3で説明した構成要素と類似するものについては同じ符号を付して説明を省略する。本実施の形態に係る半導体装置では、抵抗26が、ダイオード24とCMOS回路25との間に設けられている。それ以外は、本実施の形態に係る半導体装置は、実施の形態3に係る半導体装置と同じである。
図11は、本発明の実施の形態5に係る半導体装置の構成を示す回路図である。なお、以下、本実施の形態に係る半導体装置についての説明において、実施の形態4で説明した構成要素と類似するものについては同じ符号を付して説明を省略する。
図12は、本発明の実施の形態6に係る半導体装置の構成を示す回路図である。なお、以下、本実施の形態に係る半導体装置についての説明において、実施の形態5で説明した構成要素と類似するものについては同じ符号を付して説明を省略する。
図13は、本発明の実施の形態7に係る半導体装置の構成を示す回路図である。なお、以下、本実施の形態に係る半導体装置についての説明において、実施の形態6で説明した構成要素と類似するものについては同じ符号を付して説明を省略する。
図15は、本発明の実施の形態8に係る半導体装置の構成を示す回路図である。なお、以下、本実施の形態に係る半導体装置についての説明において、実施の形態7において図14を用いて説明した構成要素と類似するものについては同じ符号を付して説明を省略する。
図16は、本発明の実施の形態9に係る半導体装置の構成を示す回路図である。なお、以下、本実施の形態に係る半導体装置についての説明において、以上の実施の形態で説明した構成要素と類似するものについては同じ符号を付して説明を省略する。
図17は、本発明の実施の形態10に係る半導体装置の構成を示す回路図である。なお、以下、本実施の形態に係る半導体装置についての説明において、実施の形態7において図13を用いて説明した構成要素と類似するものについては同じ符号を付して説明を省略する。
Claims (16)
- 第1接続点と第2接続点との間に並列接続された主スイッチング素子と第1ダイオードとからなる並列接続体と、
前記主スイッチング素子の耐圧以下のクランプレベルを有する第1スナバデバイスと、
前記主スイッチング素子のドライブ回路に電力を供給する電力供給部の出力電圧以上のクランプレベルを有する第2スナバデバイスと
を備え、
前記第1スナバデバイスの一方端子は前記第1接続点を介して前記並列接続体の一端と接続され、前記第1スナバデバイスの他方端子は第3接続点を介して前記第2スナバデバイスの一方端子と接続され、前記第2スナバデバイスの他方端子は前記第2接続点を介して前記並列接続体の他端と接続され、
前記第2及び第3接続点を介して前記電力供給部に電力を帰還する、半導体装置。 - 請求項1に記載の半導体装置であって、
前記第3接続点と前記電力供給部との間に設けられ、前記第3接続点から前記電力供給部への向きを順方向とする第2ダイオード
をさらに備える、半導体装置。 - 請求項1または請求項2に記載の半導体装置であって、
前記第1スナバデバイスは、
前記第1スナバデバイスの前記一方端子にドレイン端子を有するとともに、前記第1スナバデバイスの前記他方端子にソース端子を有する、ワイドバンドギャップ素材からなるMOSFETと、
前記MOSFETの前記ドレイン端子及びゲート端子の間に形成されたツェナーダイオードと、
前記MOSFETの前記ソース端子及び前記ゲート端子の間に形成された第1抵抗と
を備え、
前記第2スナバデバイスは、
前記第2スナバデバイスの前記一方端子に対応するコレクタ端子と、前記第2スナバデバイスの前記他方端子に対応するエミッタ端子とを有するIGBT
を備え、
前記第2接続点から前記第1接続点への向きを前記第1ダイオードの順方向とする、半導体装置。 - 請求項3に記載の半導体装置であって、
前記第2ダイオードは、前記IGBTの寄生ダイオードである、半導体装置。 - 請求項3または請求項4に記載の半導体装置であって、
前記第2ダイオードと前記電力供給部との間に設けられた第2抵抗
をさらに備える、半導体装置。 - 請求項5に記載の半導体装置であって、
前記MOSFET及び前記IGBTの温度監視を行い、当該監視結果に基づいて前記主スイッチング素子の制御信号を生成するCMOS回路
をさらに備え、
前記CMOS回路は、前記第2ダイオード及び前記第2接続点の間に設けられ、
前記電力供給部に帰還する前記電力の一部が前記CMOS回路に供給される、半導体装置。 - 請求項6に記載の半導体装置であって、
前記第2抵抗は、前記第2ダイオードと前記CMOS回路との間に設けられている、半導体装置。 - 請求項6または請求項7に記載の半導体装置であって、
前記CMOS回路は、前記主スイッチング素子の電流検出端子の電流に基づいて信号を生成する、半導体装置。 - 請求項6乃至請求項8のいずれかに記載の半導体装置であって、
前記主スイッチング素子の温度を検出する温度検出素子
をさらに備え、
前記CMOS回路は、前記温度検出素子の検出結果に基づいて信号を生成する、半導体装置。 - 請求項6乃至請求項9のいずれかに記載の半導体装置であって、
前記CMOS回路は、前記IGBTのゲート端子の信号を監視し、当該監視結果に基づいて前記主スイッチング素子の制御信号を生成する、半導体装置。 - 請求項6乃至請求項10のいずれかに記載の半導体装置であって、
前記CMOS回路は、前記IGBTの電流検出端子の信号を監視し、当該監視結果に基づいて前記主スイッチング素子の制御信号を生成する、半導体装置。 - 請求項6乃至請求項11のいずれかに記載の半導体装置であって、
前記CMOS回路の代わりに、NMOS回路、バイポーラ回路及びBiCMOS回路のいずれか1つを備える、半導体装置。 - 請求項1乃至請求項12のいずれかに記載の半導体装置であって、
前記並列接続体の代わりにインバーターブリッジを備える、半導体装置。 - 請求項3に記載の半導体装置であって、
前記IGBT、前記ツェナーダイオード及び前記第1抵抗は、互いに個別部品である、半導体装置。 - 請求項1に記載の半導体装置と、
前記電力供給部とを備える、半導体装置。 - 請求項15に記載の半導体装置であって、
前記電力供給部は、請求項1に記載の半導体装置からから帰還された電力を、前記ドライブ回路以外の回路に供給することが可能な双方向変換器を含む、半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011124895A JP5393728B2 (ja) | 2011-06-03 | 2011-06-03 | 半導体装置 |
US13/396,934 US8570780B2 (en) | 2011-06-03 | 2012-02-15 | Semiconductor device |
CN201210066405.6A CN102810852B (zh) | 2011-06-03 | 2012-03-14 | 半导体装置 |
KR1020120056547A KR101444082B1 (ko) | 2011-06-03 | 2012-05-29 | 반도체장치 |
DE102012209284.6A DE102012209284B4 (de) | 2011-06-03 | 2012-06-01 | Halbleitervorrichtung |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011124895A JP5393728B2 (ja) | 2011-06-03 | 2011-06-03 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012253914A JP2012253914A (ja) | 2012-12-20 |
JP5393728B2 true JP5393728B2 (ja) | 2014-01-22 |
Family
ID=47173595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011124895A Active JP5393728B2 (ja) | 2011-06-03 | 2011-06-03 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8570780B2 (ja) |
JP (1) | JP5393728B2 (ja) |
KR (1) | KR101444082B1 (ja) |
CN (1) | CN102810852B (ja) |
DE (1) | DE102012209284B4 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9419597B1 (en) * | 2015-06-15 | 2016-08-16 | Analog Devices Global | Power-efficient chopping scheme for offset error correction in MEMS gyroscopes |
CN105024581B (zh) * | 2015-08-07 | 2018-03-09 | 上海沪工焊接集团股份有限公司 | Igbt全桥逆变电路 |
JP6622611B2 (ja) * | 2016-02-10 | 2019-12-18 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP6679992B2 (ja) * | 2016-03-03 | 2020-04-15 | 株式会社デンソー | 半導体装置 |
CN109755305A (zh) * | 2017-11-02 | 2019-05-14 | 华润微电子(重庆)有限公司 | 一种igbt合封单管 |
US11711025B2 (en) * | 2018-02-20 | 2023-07-25 | Mitsubishi Electric Corporation | Power semiconductor module and power conversion apparatus including the same |
JP7155990B2 (ja) * | 2018-12-17 | 2022-10-19 | 株式会社デンソー | 半導体モジュール |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2940210B2 (ja) | 1991-04-23 | 1999-08-25 | 日立工機株式会社 | リボンサブカセット |
JP3122312B2 (ja) * | 1994-07-22 | 2001-01-09 | 株式会社東芝 | 電力変換装置 |
DE19523096A1 (de) * | 1995-06-26 | 1997-01-02 | Abb Management Ag | Stromrichterschaltungsanordnung |
JPH09275674A (ja) * | 1996-04-02 | 1997-10-21 | Toshiba Corp | 電力変換装置 |
JP3649929B2 (ja) * | 1999-02-10 | 2005-05-18 | 三菱電機株式会社 | 電力変換装置 |
JP2001057772A (ja) * | 1999-08-17 | 2001-02-27 | Meidensha Corp | 静止形電力変換器 |
JP3646043B2 (ja) * | 2000-04-03 | 2005-05-11 | 東芝三菱電機産業システム株式会社 | 自励式変換器 |
JP4323073B2 (ja) * | 2000-09-11 | 2009-09-02 | 三菱電機株式会社 | パワーモジュール |
JP2002208850A (ja) * | 2000-11-13 | 2002-07-26 | Mitsubishi Electric Corp | 半導体スイッチ装置 |
CN2546245Y (zh) * | 2002-07-02 | 2003-04-23 | 四川大学 | 节能型电动车驱动装置 |
US7538997B2 (en) * | 2006-05-31 | 2009-05-26 | Alpha & Omega Semiconductor, Ltd. | Circuit configurations to reduce snapback of a transient voltage suppressor |
JP4432953B2 (ja) * | 2006-09-27 | 2010-03-17 | 株式会社日立製作所 | 半導体電力変換装置 |
CN100515911C (zh) * | 2007-02-02 | 2009-07-22 | 武汉理工大学 | 利用储能器的流动式起重机械动力装置 |
JP5280410B2 (ja) | 2010-06-21 | 2013-09-04 | 三菱電機株式会社 | 半導体装置、スナバデバイス |
-
2011
- 2011-06-03 JP JP2011124895A patent/JP5393728B2/ja active Active
-
2012
- 2012-02-15 US US13/396,934 patent/US8570780B2/en active Active
- 2012-03-14 CN CN201210066405.6A patent/CN102810852B/zh active Active
- 2012-05-29 KR KR1020120056547A patent/KR101444082B1/ko active IP Right Grant
- 2012-06-01 DE DE102012209284.6A patent/DE102012209284B4/de active Active
Also Published As
Publication number | Publication date |
---|---|
DE102012209284A1 (de) | 2012-12-06 |
CN102810852A (zh) | 2012-12-05 |
JP2012253914A (ja) | 2012-12-20 |
US8570780B2 (en) | 2013-10-29 |
KR101444082B1 (ko) | 2014-09-26 |
CN102810852B (zh) | 2016-01-13 |
US20120307532A1 (en) | 2012-12-06 |
DE102012209284B4 (de) | 2017-01-26 |
KR20120135055A (ko) | 2012-12-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5393728B2 (ja) | 半導体装置 | |
US8791744B2 (en) | Semiconductor switching system | |
US8587362B2 (en) | Gate driver and semiconductor device employing the same | |
CN103782380B (zh) | 半导体模块 | |
JP6406464B2 (ja) | 絶縁ゲート半導体装置 | |
JP4752484B2 (ja) | Dc−dcコンバータ | |
JP5157247B2 (ja) | 電力半導体装置 | |
US20160141284A1 (en) | Semiconductor device | |
JP2012090435A (ja) | 駆動回路及びこれを備える半導体装置 | |
US9178448B2 (en) | Power conversion device | |
JP2015032984A (ja) | 半導体素子の駆動装置およびそれを用いた電力変換装置 | |
EP3678287B1 (en) | Power conversion device and power conversion method | |
Otsuki et al. | Trends and opportunities in intelligent power modules (IPM) | |
JP6611989B2 (ja) | 過電流検出回路及び電力変換装置 | |
US9479049B2 (en) | Semiconductor module and boost rectifier circuit | |
JP2008072863A (ja) | 電源装置の過熱検出回路 | |
JP2005252090A (ja) | 半導体素子の温度検出方法及び電力変換装置 | |
KR101904682B1 (ko) | 전류 차단 장치 | |
JP5733138B2 (ja) | インバータ装置 | |
JP6394343B2 (ja) | 電源装置及び照明装置 | |
JP7373424B2 (ja) | 電力変換装置 | |
US20220149839A1 (en) | Semiconductor device | |
JP2018082525A (ja) | スイッチング装置 | |
CN114946124A (zh) | 半导体装置 | |
JP2020025419A (ja) | 電力変換装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130523 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130906 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130917 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131015 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5393728 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |